FranLMSP/snes
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refactor-cpu-instructions
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Author SHA1 Message Date
FranLMSP 1d08fbe19f refactor cpu decoder 2023-12-30 16:32:31 -05:00
FranLMSP 9727a753d1 fix infinite loop 2023-12-30 16:29:16 -05:00
FranLMSP 385dffe11b some fixes 2023-12-30 16:14:34 -05:00
FranLMSP c6bd426503 opcode mapper 2023-12-30 15:58:23 -05:00
FranLMSP 33b852d8d4 last instructions 2023-12-30 11:35:20 -05:00
FranLMSP 19eeff1291 more transfer instructions 2023-12-30 11:18:41 -05:00
FranLMSP 09a649c631 tcd, tcs and tdc 2023-12-30 10:32:11 -05:00
FranLMSP 124f145a44 tax and tay 2023-12-30 10:20:05 -05:00
FranLMSP 877b08fa26 stz 2023-12-30 10:05:22 -05:00
FranLMSP de2e6fb6a5 stp 2023-12-30 10:01:02 -05:00
FranLMSP a68ca8d574 st instructions 2023-12-30 09:57:02 -05:00
FranLMSP 0e8775ad6f set instructions 2023-12-30 09:23:49 -05:00
FranLMSP c620361b7a sbc 2023-12-30 09:13:18 -05:00
FranLMSP 0150d0ef7b rol, ror, rti, rtl, and rts instructions 2023-12-30 08:42:47 -05:00
FranLMSP 0eaf1ff0d6 rep 2023-12-29 23:38:57 -05:00
FranLMSP 88a47a2917 pull and push instructions 2023-12-29 23:26:37 -05:00
FranLMSP a71999ab68 mvn and mvp 2023-12-28 23:02:32 -05:00
FranLMSP 561207a299 lsr 2023-12-28 22:45:28 -05:00
FranLMSP 10f93ce3dd lda, ldx and ldy 2023-12-28 22:25:03 -05:00
FranLMSP 55fa2a5406 lda 2023-12-28 22:04:20 -05:00
FranLMSP a21b0501f3 jmp and jsr 2023-12-28 21:52:46 -05:00
FranLMSP 822cbc14ca inc 2023-12-28 21:13:06 -05:00
FranLMSP b65300792e eor 2023-12-28 21:01:33 -05:00
FranLMSP 3615799e83 dec instrs 2023-12-28 20:52:58 -05:00
FranLMSP 515ff799c8 cpx and cpy 2023-12-28 19:51:25 -05:00
FranLMSP 8c25e202e8 cop 2023-12-27 22:19:05 -05:00
FranLMSP 986a831301 cmp 2023-12-27 22:07:55 -05:00
FranLMSP a15088a0da clear instructions 2023-12-27 21:55:35 -05:00
FranLMSP fa4fa2134b bit 2023-12-27 21:43:29 -05:00
FranLMSP c0d534ed4e some branch instructions 2023-12-27 21:21:05 -05:00
FranLMSP 774010bcf7 bne 2023-12-26 22:57:23 -05:00
FranLMSP cc127890d1 beq 2023-12-26 22:52:39 -05:00
FranLMSP fa791db025 bcs 2023-12-26 22:47:22 -05:00
FranLMSP 972f3fe279 bcc 2023-12-26 22:43:16 -05:00
FranLMSP 00e87de9fe common decoding module 2023-12-26 22:27:32 -05:00
FranLMSP a1aeda38f5 asl 2023-12-26 20:24:47 -05:00
FranLMSP 826ff5480a and 2023-12-26 19:41:28 -05:00
FranLMSP 2416e85b6b adc instruction 2023-12-26 19:24:34 -05:00
FranLMSP 2e4dd7b15c decouple cycle increment logic from cpu struct (#1) 2023-12-26 03:42:07 +00:00
FranLMSP 1642d582cb add emulator screenshot 2023-12-10 14:28:31 -05:00
FranLMSP 28784f47d3 refactor DMA ticking, cpuadc chars are now visible through debug window 2023-10-07 23:33:35 -05:00
FranLMSP 7769964cf6 WIP DMA transfer logic 2023-10-07 15:32:55 -05:00
FranLMSP e701274cdb Small readability refactor 2023-10-07 11:21:37 -05:00
FranLMSP 7bdd9ab285 fix tests 2023-10-06 23:14:55 -05:00
FranLMSP 5c8bd6afca fix ldx and stx instructions and small refactor to vram 2023-10-06 23:08:03 -05:00
FranLMSP 8f05a21ebc Fix bugs with emulation mode flag 2023-10-05 16:21:33 -05:00
FranLMSP 265da3470f attempt to fix charset rendering (no success) 2023-07-10 21:43:01 -05:00
FranLMSP 703e819e80 WIP charset map render 2023-07-09 19:09:35 -05:00
FranLMSP 967cf77cc2 fix vblank nmi register and address mapping 2023-07-09 16:14:51 -05:00
FranLMSP ea7fb8ce65 define all ppu registers 2023-07-09 14:03:59 -05:00