FranLMSP/rultra64
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Author SHA1 Message Date
FranLMSP 006a0adb3b Fix 2022-02-08 09:35:28 -05:00
FranLMSP 54c00ef8d1 Merge branch 'test' of github.com:FranLMSP/rultra64 into test 2022-02-07 20:10:55 -05:00
FranLMSP a4f12a7657 Merge pull request #1 from Kim-Dewelski/main 
Hopefully this will fix stuff 📦
 2022-02-07 20:09:50 -05:00
Kim-Dewelski 4cfae27629 Removed dumb thing 2022-02-08 03:06:50 +01:00
Kim-Dewelski 92e95b0471 Moved files 2022-02-08 03:06:01 +01:00
Kim-Dewelski 359047d7f3 Good stuff! 2022-02-08 03:05:04 +01:00
FranLMSP 657e729405 Refactor (?) 2022-02-07 18:43:52 -05:00
FranLMSP a1223686e3 Parse workaround 2022-02-07 18:37:41 -05:00
FranLMSP cb01f8798c ROM loading 2022-02-07 18:11:38 -05:00
FranLMSP 398c71cb22 Tabs for registers 2022-02-07 17:40:47 -05:00
FranLMSP 48ebe8536f Demo egui app, displaying CPU Registers in a window 2022-02-07 15:26:38 -05:00
FranLMSP c421f3cf7e Small fixes 2022-02-06 20:07:07 -05:00
FranLMSP 2ac9daef97 Struct for RCP and VideoInterface registers 2022-02-04 11:24:48 -05:00
FranLMSP 9b7d829e78 HLEing boot process 2022-02-03 19:27:03 -05:00
FranLMSP 03756da4af Basic ROM implementation 2022-02-03 17:14:54 -05:00
FranLMSP 2dec06c433 mmu conditionals 2022-02-03 14:57:20 -05:00
FranLMSP c8ae274a3c Implement next_pc and refactor instruction fetching 2022-02-03 13:10:35 -05:00
FranLMSP 3d23a97a33 Refactor exec_opcode match 2022-01-19 18:26:41 -05:00
FranLMSP 067c934668 more branch instructions 2022-01-19 15:34:32 -05:00
FranLMSP 4e2fc07ca5 Some branch instructions 2022-01-17 19:41:15 -05:00
FranLMSP 7f73d99330 Some jump instructions 2022-01-16 19:41:39 -05:00
FranLMSP c1d1e284c9 More load/store instructions 2022-01-16 11:41:30 -05:00
FranLMSP 7b245275b0 Some load and store instructions 2022-01-10 21:09:49 -05:00
FranLMSP d3872f570b LWL and LWR instructions 2022-01-10 17:57:42 -05:00
FranLMSP 54bd2b106f rdram byte 8bit read write functions 2022-01-10 15:32:27 -05:00
FranLMSP d22501a37c Couple of LD instructions 2022-01-09 19:40:03 -05:00
FranLMSP a629a3f127 CP0 registers and MFC0 and MTC0 instructions 2022-01-09 17:45:40 -05:00
FranLMSP f67a74120b rdram definition 2022-01-09 13:12:35 -05:00
FranLMSP ba0394b107 Memory map definitions and virtual address convert function 2022-01-08 21:29:01 -05:00
FranLMSP 408bd64ca0 MFHI, MFLO, MTHI, MTLO instructions 2022-01-08 14:24:13 -05:00
FranLMSP a1c754d962 More bitwise instructions 2022-01-08 14:07:02 -05:00
FranLMSP 664bbc3cf4 SRLV and SLLV 2022-01-08 11:32:07 -05:00
FranLMSP 9467f99519 SRL and SRA 2022-01-05 20:07:35 -05:00
FranLMSP 5161697a92 SLL instruction 2022-01-05 19:36:39 -05:00
FranLMSP 7570616dd2 LUI instruction 2022-01-05 18:49:12 -05:00
FranLMSP f710134faf unsigned operations 2022-01-05 18:31:41 -05:00
FranLMSP ca1fc4d12c SLT and SLTU instructions 2022-01-05 18:11:40 -05:00
FranLMSP f44112991a Unsigned mult and div 2022-01-05 16:01:45 -05:00
FranLMSP 9bcea1f00e MULT instructions 2022-01-05 14:45:59 -05:00
FranLMSP 4f49d768e1 DIV and DDIV instructions 2022-01-05 14:29:06 -05:00
FranLMSP 78c0438c7d DSUB instruction 2022-01-05 11:39:55 -05:00
FranLMSP 4c4df9b78d DADD and DADDI instructions 2022-01-05 11:30:50 -05:00
FranLMSP 02c4334bfa SUB instruction 2022-01-04 20:25:03 -05:00
FranLMSP f59e925a03 ANDI instruction 2022-01-04 19:31:01 -05:00
FranLMSP 79cb0b8002 Exceptions for ADD and ADDI and AND instruction 2022-01-04 18:58:11 -05:00
FranLMSP e309906e11 ADDI 2022-01-04 15:12:01 -05:00
FranLMSP d5fa52f001 ADD instruction test 2022-01-04 13:32:04 -05:00
FranLMSP 011ed5cb97 Getters and setters for CPU registers 2022-01-04 12:06:12 -05:00
FranLMSP e3b16f9d4a First commit - define CPU, COP0 and COP1 registers 2022-01-03 11:07:01 -05:00