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006a0adb3b
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Fix
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2022-02-08 09:35:28 -05:00 |
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54c00ef8d1
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Merge branch 'test' of github.com:FranLMSP/rultra64 into test
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2022-02-07 20:10:55 -05:00 |
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a4f12a7657
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Merge pull request #1 from Kim-Dewelski/main
Hopefully this will fix stuff 📦
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2022-02-07 20:09:50 -05:00 |
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Kim-Dewelski
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4cfae27629
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Removed dumb thing
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2022-02-08 03:06:50 +01:00 |
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Kim-Dewelski
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92e95b0471
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Moved files
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2022-02-08 03:06:01 +01:00 |
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Kim-Dewelski
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359047d7f3
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Good stuff!
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2022-02-08 03:05:04 +01:00 |
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657e729405
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Refactor (?)
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2022-02-07 18:43:52 -05:00 |
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a1223686e3
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Parse workaround
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2022-02-07 18:37:41 -05:00 |
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cb01f8798c
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ROM loading
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2022-02-07 18:11:38 -05:00 |
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398c71cb22
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Tabs for registers
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2022-02-07 17:40:47 -05:00 |
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48ebe8536f
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Demo egui app, displaying CPU Registers in a window
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2022-02-07 15:26:38 -05:00 |
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c421f3cf7e
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Small fixes
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2022-02-06 20:07:07 -05:00 |
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2ac9daef97
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Struct for RCP and VideoInterface registers
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2022-02-04 11:24:48 -05:00 |
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9b7d829e78
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HLEing boot process
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2022-02-03 19:27:03 -05:00 |
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03756da4af
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Basic ROM implementation
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2022-02-03 17:14:54 -05:00 |
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2dec06c433
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mmu conditionals
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2022-02-03 14:57:20 -05:00 |
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c8ae274a3c
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Implement next_pc and refactor instruction fetching
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2022-02-03 13:10:35 -05:00 |
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3d23a97a33
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Refactor exec_opcode match
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2022-01-19 18:26:41 -05:00 |
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067c934668
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more branch instructions
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2022-01-19 15:34:32 -05:00 |
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4e2fc07ca5
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Some branch instructions
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2022-01-17 19:41:15 -05:00 |
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7f73d99330
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Some jump instructions
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2022-01-16 19:41:39 -05:00 |
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c1d1e284c9
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More load/store instructions
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2022-01-16 11:41:30 -05:00 |
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7b245275b0
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Some load and store instructions
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2022-01-10 21:09:49 -05:00 |
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d3872f570b
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LWL and LWR instructions
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2022-01-10 17:57:42 -05:00 |
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54bd2b106f
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rdram byte 8bit read write functions
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2022-01-10 15:32:27 -05:00 |
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d22501a37c
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Couple of LD instructions
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2022-01-09 19:40:03 -05:00 |
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a629a3f127
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CP0 registers and MFC0 and MTC0 instructions
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2022-01-09 17:45:40 -05:00 |
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f67a74120b
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rdram definition
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2022-01-09 13:12:35 -05:00 |
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ba0394b107
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Memory map definitions and virtual address convert function
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2022-01-08 21:29:01 -05:00 |
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408bd64ca0
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MFHI, MFLO, MTHI, MTLO instructions
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2022-01-08 14:24:13 -05:00 |
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a1c754d962
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More bitwise instructions
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2022-01-08 14:07:02 -05:00 |
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664bbc3cf4
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SRLV and SLLV
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2022-01-08 11:32:07 -05:00 |
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9467f99519
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SRL and SRA
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2022-01-05 20:07:35 -05:00 |
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5161697a92
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SLL instruction
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2022-01-05 19:36:39 -05:00 |
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7570616dd2
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LUI instruction
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2022-01-05 18:49:12 -05:00 |
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f710134faf
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unsigned operations
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2022-01-05 18:31:41 -05:00 |
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ca1fc4d12c
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SLT and SLTU instructions
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2022-01-05 18:11:40 -05:00 |
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f44112991a
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Unsigned mult and div
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2022-01-05 16:01:45 -05:00 |
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9bcea1f00e
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MULT instructions
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2022-01-05 14:45:59 -05:00 |
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4f49d768e1
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DIV and DDIV instructions
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2022-01-05 14:29:06 -05:00 |
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78c0438c7d
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DSUB instruction
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2022-01-05 11:39:55 -05:00 |
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4c4df9b78d
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DADD and DADDI instructions
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2022-01-05 11:30:50 -05:00 |
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02c4334bfa
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SUB instruction
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2022-01-04 20:25:03 -05:00 |
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f59e925a03
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ANDI instruction
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2022-01-04 19:31:01 -05:00 |
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79cb0b8002
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Exceptions for ADD and ADDI and AND instruction
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2022-01-04 18:58:11 -05:00 |
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e309906e11
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ADDI
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2022-01-04 15:12:01 -05:00 |
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d5fa52f001
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ADD instruction test
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2022-01-04 13:32:04 -05:00 |
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011ed5cb97
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Getters and setters for CPU registers
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2022-01-04 12:06:12 -05:00 |
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e3b16f9d4a
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First commit - define CPU, COP0 and COP1 registers
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2022-01-03 11:07:01 -05:00 |
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