LUI instruction

src/cpu.rs

@@ -20,6 +20,12 @@ pub fn params_rs_rt(opcode: u32) -> (usize, usize) {
     (rt as usize, rs as usize)
 }
 
+pub fn params_rt_immediate(opcode: u32) -> (usize, i16) {
+    let rt = (opcode >> 16) & 0b11111;
+    let immediate = (opcode & 0xFFFF) as i16;
+    (rt as usize, immediate)
+}
+
 pub struct CPU {
     registers: CPURegisters,
 }
@@ -208,6 +214,11 @@ impl CPU {
                 let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
                 self.sltiu(rt, rs, immediate);
             },
+            // LUI
+            0b0011_11 => {
+                let (rt, immediate) = params_rt_immediate(opcode);
+                self.lui(rt, immediate);
+            },
             _ => unimplemented!(),
         }
     }
@@ -458,6 +469,12 @@ impl CPU {
         let result = s < immediate;
         self.registers.set_by_number(rt, if result {1} else {0});
     }
+
+    pub fn lui(&mut self, rt: usize, immediate: i16) {
+        let shift = ((immediate as u16) as u32) << 16;
+        let result = (shift as i32) as i64;
+        self.registers.set_by_number(rt, result);
+    }
 }
 
 #[cfg(test)]
@@ -817,4 +834,12 @@ mod cpu_instructions_tests {
         cpu.sltiu(reg_t, reg_s, 321);
         assert_eq!(cpu.registers.get_by_number(reg_t), 1);
     }
+
+    #[test]
+    fn test_lui() {
+        let mut cpu = CPU::new();
+        let reg_t = 20;
+        cpu.lui(reg_t, -10);
+        assert_eq!(cpu.registers.get_by_number(reg_t), -655360);
+    }
 }