Commit Graph

Select branches

Hide Pull Requests

main

test

#1

Mono Color

• 006a0adb3b Fix main Franco Colmenarez 2022-02-07 20:13:01 -05:00
• 2b83694ec6 asdasdasd test Franco Colmenarez 2022-02-07 20:13:01 -05:00
• 54c00ef8d1 Merge branch 'test' of github.com:FranLMSP/rultra64 into test Franco Colmenarez 2022-02-07 20:10:55 -05:00
• a4f12a7657 Merge pull request #1 from Kim-Dewelski/main Franco 2022-02-07 20:09:50 -05:00
• 4cfae27629 Removed dumb thing Kim-Dewelski 2022-02-08 03:06:50 +01:00
• 92e95b0471 Moved files Kim-Dewelski 2022-02-08 03:06:01 +01:00
• 359047d7f3 Good stuff! Kim-Dewelski 2022-02-08 03:05:04 +01:00
• 657e729405 Refactor (?) Franco Colmenarez 2022-02-07 18:43:52 -05:00
• a1223686e3 Parse workaround Franco Colmenarez 2022-02-07 18:37:41 -05:00
• cb01f8798c ROM loading Franco Colmenarez 2022-02-07 18:11:38 -05:00
• 398c71cb22 Tabs for registers Franco Colmenarez 2022-02-07 17:40:47 -05:00
• 48ebe8536f Demo egui app, displaying CPU Registers in a window Franco Colmenarez 2022-02-07 15:26:38 -05:00
• c421f3cf7e Small fixes Franco Colmenarez 2022-02-06 20:07:07 -05:00
• 2ac9daef97 Struct for RCP and VideoInterface registers Franco Colmenarez 2022-02-04 11:24:48 -05:00
• 9b7d829e78 HLEing boot process Franco Colmenarez 2022-02-03 19:27:03 -05:00
• 03756da4af Basic ROM implementation Franco Colmenarez 2022-02-03 17:14:54 -05:00
• 2dec06c433 mmu conditionals Franco Colmenarez 2022-02-03 14:54:24 -05:00
• c8ae274a3c Implement next_pc and refactor instruction fetching Franco Colmenarez 2022-02-03 13:10:35 -05:00
• 3d23a97a33 Refactor exec_opcode match Franco Colmenarez 2022-01-19 18:26:41 -05:00
• 067c934668 more branch instructions Franco Colmenarez 2022-01-19 15:34:32 -05:00
• 4e2fc07ca5 Some branch instructions Franco Colmenarez 2022-01-17 18:29:08 -05:00
• 7f73d99330 Some jump instructions Franco Colmenarez 2022-01-16 19:41:39 -05:00
• c1d1e284c9 More load/store instructions Franco Colmenarez 2022-01-16 11:41:30 -05:00
• 7b245275b0 Some load and store instructions Franco Colmenarez 2022-01-10 21:09:49 -05:00
• d3872f570b LWL and LWR instructions Franco Colmenarez 2022-01-10 17:57:42 -05:00
• 54bd2b106f rdram byte 8bit read write functions Franco Colmenarez 2022-01-10 15:32:27 -05:00
• d22501a37c Couple of LD instructions Franco Colmenarez 2022-01-09 19:40:03 -05:00
• a629a3f127 CP0 registers and MFC0 and MTC0 instructions Franco Colmenarez 2022-01-09 17:45:40 -05:00
• f67a74120b rdram definition Franco Colmenarez 2022-01-09 13:12:35 -05:00
• ba0394b107 Memory map definitions and virtual address convert function Franco Colmenarez 2022-01-08 21:29:01 -05:00
• 408bd64ca0 MFHI, MFLO, MTHI, MTLO instructions Franco Colmenarez 2022-01-08 14:24:13 -05:00
• a1c754d962 More bitwise instructions Franco Colmenarez 2022-01-08 14:07:02 -05:00
• 664bbc3cf4 SRLV and SLLV Franco Colmenarez 2022-01-08 11:29:55 -05:00
• 9467f99519 SRL and SRA Franco Colmenarez 2022-01-05 20:07:35 -05:00
• 5161697a92 SLL instruction Franco Colmenarez 2022-01-05 19:36:39 -05:00
• 7570616dd2 LUI instruction Franco Colmenarez 2022-01-05 18:49:12 -05:00
• f710134faf unsigned operations Franco Colmenarez 2022-01-05 18:31:41 -05:00
• ca1fc4d12c SLT and SLTU instructions Franco Colmenarez 2022-01-05 18:11:40 -05:00
• f44112991a Unsigned mult and div Franco Colmenarez 2022-01-05 16:01:45 -05:00
• 9bcea1f00e MULT instructions Franco Colmenarez 2022-01-05 14:45:59 -05:00
• 4f49d768e1 DIV and DDIV instructions Franco Colmenarez 2022-01-05 14:12:10 -05:00
• 78c0438c7d DSUB instruction Franco Colmenarez 2022-01-05 11:39:55 -05:00
• 4c4df9b78d DADD and DADDI instructions Franco Colmenarez 2022-01-05 11:30:50 -05:00
• 02c4334bfa SUB instruction Franco Colmenarez 2022-01-04 20:25:03 -05:00
• f59e925a03 ANDI instruction Franco Colmenarez 2022-01-04 19:31:01 -05:00
• 79cb0b8002 Exceptions for ADD and ADDI and AND instruction Franco Colmenarez 2022-01-04 18:58:11 -05:00
• e309906e11 ADDI Franco Colmenarez 2022-01-04 15:12:01 -05:00
• d5fa52f001 ADD instruction test Franco Colmenarez 2022-01-04 13:32:04 -05:00
• 011ed5cb97 Getters and setters for CPU registers Franco Colmenarez 2022-01-04 12:06:12 -05:00
• e3b16f9d4a First commit - define CPU, COP0 and COP1 registers Franco Colmenarez 2022-01-03 11:06:22 -05:00