mirror of
https://github.com/FranLMSP/rultra64.git
synced 2026-01-01 07:51:34 -05:00
Refactor exec_opcode match
This commit is contained in:
527
src/cpu.rs
527
src/cpu.rs
@@ -98,18 +98,32 @@ impl CPU {
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let inst = bytes[0] >> 2;
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match inst {
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// SPECIAL
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0b0000_00 => {
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match opcode & 0b111_1111_1111 {
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0b000000 => {
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match opcode & 0b111111 {
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// ADD
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0b000_0010_0000 => {
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0b100000 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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let res = self.add(rd, rs, rt);
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if let Err(_) = res {
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todo!("Throw exception for add overflow ADD");
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}
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},
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// ADDU
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0b100001 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.addu(rd, rs, rt);
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},
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// AND
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0b100100 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.and(rd, rs, rt);
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},
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// BREAK
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0b001101 => {
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todo!("BREAK instruction");
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},
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// DADD
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0b000_0010_1100 => {
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0b101100 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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let res = self.dadd(rd, rs, rt);
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if let Err(_) = res {
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@@ -117,30 +131,87 @@ impl CPU {
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}
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},
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// DADDU
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0b000_0010_1101 => {
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0b101101 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.daddu(rd, rs, rt);
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},
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// ADDU
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0b000_0010_0001 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.addu(rd, rs, rt);
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// DDIV
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0b011110 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.ddiv(rs, rt);
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},
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// SUB
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0b000_0010_0010 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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let res = self.sub(rd, rs, rt);
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if let Err(_) = res {
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todo!("Throw exception for sub overflow SUB");
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}
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// DDIVU
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0b011111 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.ddivu(rs, rt);
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},
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// SUBU
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0b000_0010_0011 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.subu(rd, rs, rt);
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// DIV
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0b011010 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.div(rs, rt);
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},
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// DIVU
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0b011011 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.divu(rs, rt);
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},
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// DMULT
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0b011100 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.dmult(rs, rt);
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},
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// DMULTU
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0b011101 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.dmultu(rs, rt);
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},
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// DSLL
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0b111000 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsll(rd, rt, sa);
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},
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// DSLLV
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0b010100 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsllv(rd, rt, rs);
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},
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// DSLL32
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0b111100 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsll32(rd, rt, sa);
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},
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// DSRA
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0b111011 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsra(rd, rt, rs);
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},
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// DSRAV
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0b010111 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsrav(rd, rt, rs);
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},
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// DSRA32
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0b111111 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsra32(rd, rt, sa);
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},
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// DSRL
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0b111010 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsrl(rd, rt, sa);
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},
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// DSRLV
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0b010110 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsrlv(rd, rt, rs);
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},
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// DSRL32
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0b111110 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsrl32(rd, rt, sa);
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},
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// DSUB
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0b000_0010_1110 => {
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0b101110 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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let res = self.dsub(rd, rs, rt);
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if let Err(_) = res {
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@@ -148,174 +219,136 @@ impl CPU {
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}
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},
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// DSUBU
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0b000_0010_1111 => {
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0b101111 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.dsubu(rd, rs, rt);
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},
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// DIV
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0b000_0001_1010 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.div(rs, rt);
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},
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// DIVU
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0b000_0001_1011 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.divu(rs, rt);
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},
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// DDIV
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0b000_0001_1110 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.ddiv(rs, rt);
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},
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// DDIVU
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0b000_0001_1111 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.ddivu(rs, rt);
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},
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// MULT
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0b000_0001_1000 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.mult(rs, rt);
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},
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// MULTU
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0b000_0001_1001 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.multu(rs, rt);
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},
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// DMULT
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0b000_0001_1100 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.dmult(rs, rt);
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},
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// DMULTU
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0b000_0001_1101 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.dmultu(rs, rt);
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},
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// AND
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0b000_0010_0100 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.and(rd, rs, rt);
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},
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// OR
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0b000_0010_0101 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.or(rd, rs, rt);
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},
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// NOR
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0b000_0010_0111 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.nor(rd, rs, rt);
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},
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// SLT
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0b000_0010_1010 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.slt(rd, rs, rt);
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},
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// SLTU
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0b000_0010_1011 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.slt(rd, rs, rt);
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},
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// SLL
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0b000_0000_0000 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.sll(rd, rt, sa);
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},
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// SRL
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0b000_0000_0010 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.srl(rd, rt, sa);
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},
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// SRA
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0b000_0000_0011 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.sra(rd, rt, sa);
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},
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// SLLV
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0b000_0000_0100 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.sllv(rd, rt, rs);
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},
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// SRL
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0b000_0000_0110 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.sllv(rd, rt, rs);
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},
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// SRAV
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0b000_0000_0111 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.sllv(rd, rt, rs);
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},
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// DSLL
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0b000_0011_1000 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsll(rd, rt, sa);
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},
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// DSRL
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0b000_0011_1010 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsrl(rd, rt, sa);
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},
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// DSRA
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0b000_0011_1011 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsra(rd, rt, rs);
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},
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// DSLLV
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0b000_0001_0100 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsllv(rd, rt, rs);
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},
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// DSRLV
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0b000_0001_0110 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsrlv(rd, rt, rs);
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},
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// DSRAV
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0b000_0001_0111 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.dsrav(rd, rt, rs);
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},
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// DSLL32
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0b000_0011_1100 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsll32(rd, rt, sa);
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},
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// DSRL32
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0b000_0011_1110 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsrl32(rd, rt, sa);
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},
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// DSRA32
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0b000_0011_1111 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.dsra32(rd, rt, sa);
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},
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// MFHI
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0b000_0001_0000 => self.mfhi(params_rd(opcode)),
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// MFLO
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0b000_0001_0010 => self.mflo(params_rd(opcode)),
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// MTHI
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0b000_0001_0001 => self.mthi(params_rs(opcode)),
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// MTLO
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0b000_0001_0011 => self.mtlo(params_rs(opcode)),
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// JALR
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0b000_0000_1001 => {
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0b001001 => {
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let rd = (opcode >> 10) & 0x7FF;
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let rs = (opcode >> 21) & 0x7FF;
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self.jalr(rd as usize, rs as usize);
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},
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// JR
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0b000_0000_1000 => {
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0b001000 => {
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let rs = (opcode >> 21) & 0x7FF;
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self.jr(rs as usize);
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},
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// MFHI
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0b010000 => self.mfhi(params_rd(opcode)),
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// MFLO
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0b010010 => self.mflo(params_rd(opcode)),
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// MTHI
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0b010001 => self.mthi(params_rs(opcode)),
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// MTLO
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0b010011 => self.mtlo(params_rs(opcode)),
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// MULT
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0b011000 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.mult(rs, rt);
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},
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// MULTU
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0b011001 => {
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let (rs, rt) = params_rs_rt(opcode);
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self.multu(rs, rt);
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},
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// NOR
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0b100111 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.nor(rd, rs, rt);
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},
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// OR
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0b100101 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.or(rd, rs, rt);
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},
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// SLL
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0b000000 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.sll(rd, rt, sa);
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},
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// SLLV
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0b000100 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.sllv(rd, rt, rs);
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},
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// SLT
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0b101010 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.slt(rd, rs, rt);
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},
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// SLTU
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0b101011 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.slt(rd, rs, rt);
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},
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// SRA
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0b000011 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.sra(rd, rt, sa);
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},
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// SRAV
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0b000111 => {
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let (rd, rt, rs) = params_rd_rt_rs(opcode);
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self.srav(rd, rt, rs);
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},
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// SRL
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0b000010 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.srl(rd, rt, sa);
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},
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// SRLV
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0b000110 => {
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let (rd, rt, sa) = params_rd_rt_sa(opcode);
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self.srlv(rd, rt, sa);
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},
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// SUB
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0b100010 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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let res = self.sub(rd, rs, rt);
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if let Err(_) = res {
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todo!("Throw exception for sub overflow SUB");
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}
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},
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// SUBU
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0b100011 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.subu(rd, rs, rt);
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},
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// SYNC
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0b001111 => {
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},
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// SYSCALL
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0b001100 => {
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},
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// TEQ
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0b110100 => {
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},
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// TGE
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0b110000 => {
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},
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// TGEU
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0b110001 => {
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},
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// TLT
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0b110010 => {
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},
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// TLTU
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0b110011 => {
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},
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// TNE
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0b110110 => {
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},
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// XOR
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0b100110 => {
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let (rd, rs, rt) = params_rd_rs_rt(opcode);
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self.xor(rd, rs, rt);
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},
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_ => unimplemented!(),
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};
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},
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// REGIMM
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0b0000_01 => {
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0b000001 => {
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match (opcode >> 16) & 0b11111 {
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// BGEZ
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0b00001 => {
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@@ -357,11 +390,29 @@ impl CPU {
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let (rs, offset) = params_rs_offset(opcode);
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self.bltzl(rs, offset);
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},
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// TEQI
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0b01100 => {
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},
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// TGEI
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0b01000 => {
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},
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// TGEIU
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0b01001 => {
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},
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// TLTI
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0b01010 => {
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},
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// TLTIU
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0b01011 => {
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},
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// TNEI
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0b01110 => {
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},
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_ => unimplemented!(),
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}
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};
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},
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// DADDI
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0b0110_00 => {
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0b011000 => {
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let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
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let res = self.daddi(rt, rs, immediate);
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if inst == 0b0110_00 {
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@@ -371,12 +422,12 @@ impl CPU {
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}
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},
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// DADDIU
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0b0110_01 => {
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0b011001 => {
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let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
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self.daddiu(rt, rs, immediate);
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},
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// ADDI
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0b0010_00 => {
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0b001000 => {
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let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
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let res = self.addi(rt, rs, immediate);
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if inst == 0b0010_00 {
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@@ -386,200 +437,218 @@ impl CPU {
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}
|
||||
},
|
||||
// ADDIU
|
||||
0b0010_01 => {
|
||||
0b001001 => {
|
||||
let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
|
||||
self.addiu(rt, rs, immediate);
|
||||
},
|
||||
// ANDI
|
||||
0b0011_00 => {
|
||||
0b001100 => {
|
||||
let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
|
||||
self.andi(rt, rs, immediate);
|
||||
},
|
||||
// ORI
|
||||
0b0011_01 => {
|
||||
0b001101 => {
|
||||
let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
|
||||
self.ori(rt, rs, immediate);
|
||||
},
|
||||
// SLTI
|
||||
0b0010_10 => {
|
||||
0b001010 => {
|
||||
let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
|
||||
self.slti(rt, rs, immediate);
|
||||
},
|
||||
// SLTIU
|
||||
0b0010_11 => {
|
||||
0b001011 => {
|
||||
let (rt, rs, immediate) = params_rt_rs_immediate(opcode);
|
||||
self.sltiu(rt, rs, immediate);
|
||||
},
|
||||
// LUI
|
||||
0b0011_11 => {
|
||||
0b001111 => {
|
||||
let (rt, immediate) = params_rt_immediate(opcode);
|
||||
self.lui(rt, immediate);
|
||||
},
|
||||
// COP0
|
||||
0b0100_00 => {
|
||||
let instr = (opcode >> 21) & 11;
|
||||
match instr {
|
||||
// MTC0
|
||||
0b0100_0000_100 => {
|
||||
let (rt, rd) = params_rt_rd(opcode);
|
||||
self.mtc0(rt, rd);
|
||||
},
|
||||
// MFC0
|
||||
0b0100_0000_000 => {
|
||||
let (rt, rd) = params_rt_rd(opcode);
|
||||
self.mfc0(rt, rd);
|
||||
},
|
||||
// DMTC0
|
||||
0b0100_0000_101 => {
|
||||
let (rt, rd) = params_rt_rd(opcode);
|
||||
self.dmtc0(rt, rd);
|
||||
},
|
||||
0b010000 => {
|
||||
match (opcode >> 21) & 0b11111 {
|
||||
// DMFC0
|
||||
0b0100_0000_001 => {
|
||||
0b00001 => {
|
||||
let (rt, rd) = params_rt_rd(opcode);
|
||||
self.dmfc0(rt, rd);
|
||||
},
|
||||
_ => unimplemented!(),
|
||||
// DMTC0
|
||||
0b00101 => {
|
||||
let (rt, rd) = params_rt_rd(opcode);
|
||||
self.dmtc0(rt, rd);
|
||||
},
|
||||
// MFC0
|
||||
0b00000 => {
|
||||
let (rt, rd) = params_rt_rd(opcode);
|
||||
self.mfc0(rt, rd);
|
||||
},
|
||||
// MTC0
|
||||
0b00100 => {
|
||||
let (rt, rd) = params_rt_rd(opcode);
|
||||
self.mtc0(rt, rd);
|
||||
},
|
||||
_ => {
|
||||
match opcode & 0b111111 {
|
||||
// ERET
|
||||
0b011000 => {
|
||||
},
|
||||
// TLBP
|
||||
0b001000 => {
|
||||
},
|
||||
// TLBR
|
||||
0b000001 => {
|
||||
},
|
||||
// TLBWI
|
||||
0b000010 => {
|
||||
},
|
||||
// TLBWR
|
||||
0b000110 => {
|
||||
},
|
||||
_ => unimplemented!(),
|
||||
};
|
||||
},
|
||||
};
|
||||
},
|
||||
// LB
|
||||
0b1000_00 => {
|
||||
0b100000 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lb(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LBU
|
||||
0b1001_00 => {
|
||||
0b100100 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lbu(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LH
|
||||
0b1000_01 => {
|
||||
0b100001 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lh(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LHU
|
||||
0b1001_01 => {
|
||||
0b100101 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lhu(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LW
|
||||
0b1000_11 => {
|
||||
0b100011 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lw(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LWL
|
||||
0b1000_10 => {
|
||||
0b100010 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lwl(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LWR
|
||||
0b1001_10 => {
|
||||
0b100110 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lwr(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SB
|
||||
0b1010_00 => {
|
||||
0b101000 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.sb(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SH
|
||||
0b1010_01 => {
|
||||
0b101001 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.sh(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SW
|
||||
0b1010_11 => {
|
||||
0b101011 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.sw(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SWL
|
||||
0b1010_10 => {
|
||||
0b101010 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.swl(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SWR
|
||||
0b1011_00 => {
|
||||
0b101100 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.swr(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LLD
|
||||
0b1101_00 => {
|
||||
0b110100 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lld(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// LWU
|
||||
0b1001_11 => {
|
||||
0b100111 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.lwu(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SC
|
||||
0b1110_00 => {
|
||||
0b111000 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.sc(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SCD
|
||||
0b1111_00 => {
|
||||
0b111100 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.scd(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// SD
|
||||
0b1111_11 => {
|
||||
0b111111 => {
|
||||
// let (rt, offset, base) = params_rt_offset_base(opcode);
|
||||
// self.sd(rt, offset, base, mmu);
|
||||
todo!("Receive MMU parameter");
|
||||
},
|
||||
// J
|
||||
0b0000_10 => self.j(params_target(opcode)),
|
||||
0b000010 => self.j(params_target(opcode)),
|
||||
// JAL
|
||||
0b0011_10 => self.jal(params_target(opcode)),
|
||||
0b001110 => self.jal(params_target(opcode)),
|
||||
// BEQ
|
||||
0b0001_00 => {
|
||||
0b000100 => {
|
||||
let (rs, rt, offset) = params_rs_rt_offset(opcode);
|
||||
self.beq(rs, rt, offset);
|
||||
},
|
||||
// BGTZ
|
||||
0b0001_11 => {
|
||||
0b000111 => {
|
||||
let (rs, offset) = params_rs_offset(opcode);
|
||||
self.bgtz(rs, offset);
|
||||
},
|
||||
// BGTZL
|
||||
0b0101_11 => {
|
||||
0b010111 => {
|
||||
let (rs, offset) = params_rs_offset(opcode);
|
||||
self.bgtzl(rs, offset);
|
||||
},
|
||||
// BLEZ
|
||||
0b0001_10 => {
|
||||
0b000110 => {
|
||||
let (rs, offset) = params_rs_offset(opcode);
|
||||
self.blez(rs, offset);
|
||||
},
|
||||
// BLEZL
|
||||
0b0101_10 => {
|
||||
0b010110 => {
|
||||
let (rs, offset) = params_rs_offset(opcode);
|
||||
self.blezl(rs, offset);
|
||||
},
|
||||
// BNE
|
||||
0b0001_01 => {
|
||||
0b000101 => {
|
||||
let (rs, rt, offset) = params_rs_rt_offset(opcode);
|
||||
self.bne(rs, rt, offset);
|
||||
},
|
||||
// BNEL
|
||||
0b0001_01 => {
|
||||
0b010101 => {
|
||||
let (rs, rt, offset) = params_rs_rt_offset(opcode);
|
||||
self.bnel(rs, rt, offset);
|
||||
},
|
||||
|
||||
Reference in New Issue
Block a user