FranLMSP/rultra64
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5161697a92d63cb853c63cc84b0493fdb465af5a
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Author SHA1 Message Date
FranLMSP 5161697a92 SLL instruction 2022-01-05 19:36:39 -05:00
FranLMSP 7570616dd2 LUI instruction 2022-01-05 18:49:12 -05:00
FranLMSP f710134faf unsigned operations 2022-01-05 18:31:41 -05:00
FranLMSP ca1fc4d12c SLT and SLTU instructions 2022-01-05 18:11:40 -05:00
FranLMSP f44112991a Unsigned mult and div 2022-01-05 16:01:45 -05:00
FranLMSP 9bcea1f00e MULT instructions 2022-01-05 14:45:59 -05:00
FranLMSP 4f49d768e1 DIV and DDIV instructions 2022-01-05 14:29:06 -05:00
FranLMSP 78c0438c7d DSUB instruction 2022-01-05 11:39:55 -05:00
FranLMSP 4c4df9b78d DADD and DADDI instructions 2022-01-05 11:30:50 -05:00
FranLMSP 02c4334bfa SUB instruction 2022-01-04 20:25:03 -05:00
FranLMSP f59e925a03 ANDI instruction 2022-01-04 19:31:01 -05:00
FranLMSP 79cb0b8002 Exceptions for ADD and ADDI and AND instruction 2022-01-04 18:58:11 -05:00
FranLMSP e309906e11 ADDI 2022-01-04 15:12:01 -05:00
FranLMSP d5fa52f001 ADD instruction test 2022-01-04 13:32:04 -05:00
FranLMSP 011ed5cb97 Getters and setters for CPU registers 2022-01-04 12:06:12 -05:00
FranLMSP e3b16f9d4a First commit - define CPU, COP0 and COP1 registers 2022-01-03 11:07:01 -05:00