clippy fix

This commit is contained in:
2024-01-15 21:50:50 -05:00
parent 3992529a71
commit e2446514db
116 changed files with 378 additions and 409 deletions

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@@ -22,3 +22,5 @@ jobs:
run: cargo build --verbose
- name: Run tests
run: cargo test --verbose
- name: Run Clippy
run: cargo clippy --all-targets --all-features

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@@ -18,4 +18,4 @@ pub enum Flags {
pub enum ModeFlag {
Carry,
EmulationMode,
}
}

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@@ -34,7 +34,7 @@ impl Bus {
}
fn read_wram(&self, address: u32) -> u8 {
return self.wram[(address & 0xFFFF) as usize];
self.wram[(address & 0xFFFF) as usize]
}
fn write_wram(&mut self, address: u32, value: u8) {
@@ -110,6 +110,12 @@ impl Bus {
}
}
impl Default for Bus {
fn default() -> Self {
Self::new()
}
}
#[cfg(test)]
mod bus_tests {

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@@ -53,9 +53,8 @@ fn common_conditions(cpu_registers: &Registers, addressing_mode: AddressingMode,
Condition::MemorySelectFlag => {
if cpu_registers.is_16bit_mode() {
cycles += 1;
match addressing_mode {
A::Immediate => bytes += 1,
_ => {},
if let A::Immediate = addressing_mode {
bytes += 1
}
}
},

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@@ -47,7 +47,7 @@ pub enum TransferFormat {
FourBytesFourRegisters, // Write once
}
pub struct DMATransferProps {
#[allow(dead_code)] pub struct DMATransferProps {
channel: DMAChannel,
channel_number: u8,
direction: TransferDirection,
@@ -119,15 +119,15 @@ impl DMATransferProps {
DMATransferProps::read_channel_register(registers, DASXL, channel_number) as u16;
Self {
channel: channel,
channel_number: channel_number,
direction: direction,
addressing_mode: addressing_mode,
auto_update_a_address: auto_update_a_address,
transfer_format: transfer_format,
a_bus_address: a_bus_address,
b_bus_address: b_bus_address,
number_of_bytes: number_of_bytes,
channel,
channel_number,
direction,
addressing_mode,
auto_update_a_address,
transfer_format,
a_bus_address,
b_bus_address,
number_of_bytes,
}
}
@@ -245,8 +245,8 @@ impl DMA {
pub fn prepare_dma_transfer(&mut self, dma_select: u8) {
self.active_dma_transfers = Vec::new();
let mut active_channels = [false; 8];
for i in 0..8 {
active_channels[i] = (dma_select & (1 << i)) != 0;
for (i, active_channel) in active_channels.iter_mut().enumerate() {
*active_channel = (dma_select & (1 << i)) != 0;
}
for (channel, is_active) in active_channels.iter().enumerate() {
@@ -284,4 +284,10 @@ impl DMA {
}
pending_bus_writes
}
}
}
impl Default for DMA {
fn default() -> Self {
Self::new()
}
}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16bit_from_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "ADC";
static INSTR_NAME: &str = "ADC";
pub struct ADC {
pub addressing_mode: AddressingMode,
@@ -51,7 +51,7 @@ impl CPUInstruction for ADC8BIN {
);
registers.set_low_a(result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -73,7 +73,7 @@ impl CPUInstruction for ADC16BIN {
);
registers.a = result;
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -95,7 +95,7 @@ impl CPUInstruction for ADC8BCD {
);
registers.set_low_a(result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -117,7 +117,7 @@ impl CPUInstruction for ADC16BCD {
);
registers.a = result;
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16bit_from_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "AND";
static INSTR_NAME: &str = "AND";
pub struct AND {
pub addressing_mode: AddressingMode,
@@ -43,7 +43,7 @@ impl CPUInstruction for AND8 {
);
registers.set_low_a(result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_bitwise(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bitwise(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -64,7 +64,7 @@ impl CPUInstruction for AND16 {
);
registers.a = result;
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_bitwise(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bitwise(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "ASL";
static INSTR_NAME: &str = "ASL";
pub struct ASL {
pub addressing_mode: AddressingMode,
@@ -42,7 +42,7 @@ impl CPUInstruction for ASL8 {
);
registers.set_low_a(result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_bitwise(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bitwise(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -62,7 +62,7 @@ impl CPUInstruction for ASL16 {
);
registers.a = result;
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_bitwise(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bitwise(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BCC";
static INSTR_NAME: &str = "BCC";
pub struct BCC {}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BCS";
static INSTR_NAME: &str = "BCS";
pub struct BCS {}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BEQ";
static INSTR_NAME: &str = "BEQ";
pub struct BEQ {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, bit_common, read_write_common::{read_8bit_from_address, read_16bit_from_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "BIT";
static INSTR_NAME: &str = "BIT";
pub struct BIT {
pub addressing_mode: AddressingMode,
@@ -43,7 +43,7 @@ impl CPUInstruction for BIT8 {
read_8bit_from_address(registers, bus, self.addressing_mode),
self.addressing_mode,
);
let (bytes, cycles) = cycles::increment_cycles_bit(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bit(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -64,7 +64,7 @@ impl CPUInstruction for BIT16 {
read_16bit_from_address(registers, bus, self.addressing_mode),
self.addressing_mode,
);
let (bytes, cycles) = cycles::increment_cycles_bit(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bit(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BMI";
static INSTR_NAME: &str = "BMI";
pub struct BMI {}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BNE";
static INSTR_NAME: &str = "BNE";
pub struct BNE {}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BPL";
static INSTR_NAME: &str = "BPL";
pub struct BPL {}

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@@ -5,7 +5,7 @@ use super::decoder_common;
use super::branch_common;
use crate::cpu::cycles;
static INSTR_NAME: &'static str = "BRA";
static INSTR_NAME: &str = "BRA";
pub struct BRA {}

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@@ -22,6 +22,5 @@ pub fn do_branch(nearlabel: u8, registers: &mut Registers) -> bool {
registers.increment_pc(nearlabel as u16);
}
let new_pc = registers.get_pc_address();
let page_boundary_crossed = (old_pc & 0xFF00) != (new_pc & 0xFF00);
return page_boundary_crossed
(old_pc & 0xFF00) != (new_pc & 0xFF00)
}

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@@ -5,7 +5,7 @@ use super::decoder_common;
use super::push_common;
use crate::cpu::cycles;
static INSTR_NAME: &'static str = "BRK";
static INSTR_NAME: &str = "BRK";
pub struct BRK {}
@@ -24,13 +24,3 @@ impl CPUInstruction for BRK {
decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
}
}
#[cfg(test)]
mod cpu_instructions_tests {
use super::*;
#[test]
fn test() {
}
}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use crate::cpu::cycles;
static INSTR_NAME: &'static str = "BRL";
static INSTR_NAME: &str = "BRL";
pub struct BRL {}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BVC";
static INSTR_NAME: &str = "BVC";
pub struct BVC {}

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@@ -4,7 +4,7 @@ use super::CPUInstruction;
use super::decoder_common;
use super::branch_common;
static INSTR_NAME: &'static str = "BVS";
static INSTR_NAME: &str = "BVS";
pub struct BVS {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "CLC";
static INSTR_NAME: &str = "CLC";
pub struct CLC {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "CLD";
static INSTR_NAME: &str = "CLD";
pub struct CLD {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "CLI";
static INSTR_NAME: &str = "CLI";
pub struct CLI {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "CLV";
static INSTR_NAME: &str = "CLV";
pub struct CLV {}

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@@ -5,7 +5,7 @@ use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16b
use super::decoder_common;
use super::comp_common;
static INSTR_NAME: &'static str = "CMP";
static INSTR_NAME: &str = "CMP";
pub struct CMP {
pub addressing_mode: AddressingMode,
@@ -43,7 +43,7 @@ impl CPUInstruction for CMP8 {
registers.a as u8,
read_8bit_from_address(registers, bus, self.addressing_mode),
);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -63,7 +63,7 @@ impl CPUInstruction for CMP16 {
registers.a,
read_16bit_from_address(registers, bus, self.addressing_mode),
);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -5,7 +5,7 @@ use super::decoder_common;
use super::push_common;
use crate::cpu::cycles;
static INSTR_NAME: &'static str = "COP";
static INSTR_NAME: &str = "COP";
pub struct COP {}
@@ -24,13 +24,3 @@ impl CPUInstruction for COP {
decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
}
}
#[cfg(test)]
mod cpu_instructions_tests {
use super::*;
#[test]
fn test() {
}
}

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@@ -5,7 +5,7 @@ use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16b
use super::decoder_common;
use super::comp_common;
static INSTR_NAME: &'static str = "CPX";
static INSTR_NAME: &str = "CPX";
pub struct CPX {
pub addressing_mode: AddressingMode,
@@ -43,7 +43,7 @@ impl CPUInstruction for CPX8 {
registers.x as u8,
read_8bit_from_address(registers, bus, self.addressing_mode),
);
let (bytes, cycles) = cycles::increment_cycles_comp_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_comp_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -63,7 +63,7 @@ impl CPUInstruction for CPX16 {
registers.x,
read_16bit_from_address(registers, bus, self.addressing_mode),
);
let (bytes, cycles) = cycles::increment_cycles_comp_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_comp_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -5,7 +5,7 @@ use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16b
use super::decoder_common;
use super::comp_common;
static INSTR_NAME: &'static str = "CPY";
static INSTR_NAME: &str = "CPY";
pub struct CPY {
pub addressing_mode: AddressingMode,
@@ -43,7 +43,7 @@ impl CPUInstruction for CPY8 {
registers.y as u8,
read_8bit_from_address(registers, bus, self.addressing_mode),
);
let (bytes, cycles) = cycles::increment_cycles_comp_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_comp_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -63,7 +63,7 @@ impl CPUInstruction for CPY16 {
registers.y,
read_16bit_from_address(registers, bus, self.addressing_mode),
);
let (bytes, cycles) = cycles::increment_cycles_comp_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_comp_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, dec_common, read_write_common::{read_8bit_from_address, write_8bit_to_address, read_16bit_from_address, write_16bit_to_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "DEC";
static INSTR_NAME: &str = "DEC";
pub struct DEC {
pub addressing_mode: AddressingMode,
@@ -42,7 +42,7 @@ impl CPUInstruction for DEC8 {
read_8bit_from_address(registers, bus, self.addressing_mode),
) as u8;
write_8bit_to_address(registers, bus, self.addressing_mode, result);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -62,7 +62,7 @@ impl CPUInstruction for DEC16 {
read_16bit_from_address(registers, bus, self.addressing_mode),
) as u16;
write_16bit_to_address(registers, bus, self.addressing_mode, result);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, dec_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "DEX";
static INSTR_NAME: &str = "DEX";
pub struct DEX {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, dec_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "DEY";
static INSTR_NAME: &str = "DEY";
pub struct DEY {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16bit_from_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "EOR";
static INSTR_NAME: &str = "EOR";
pub struct EOR {
pub addressing_mode: AddressingMode,
@@ -41,7 +41,7 @@ impl CPUInstruction for EOR8 {
let (result, affected_flags) = alu::eor(registers.a as u8, value);
registers.set_low_a(result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_bitwise(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bitwise(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -60,7 +60,7 @@ impl CPUInstruction for EOR16 {
let (result, affected_flags) = alu::eor(registers.a, value);
registers.a = result;
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_bitwise(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_bitwise(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, dec_common, read_write_common::{read_8bit_from_address, write_8bit_to_address, read_16bit_from_address, write_16bit_to_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "INC";
static INSTR_NAME: &str = "INC";
pub struct INC {
pub addressing_mode: AddressingMode,
@@ -42,7 +42,7 @@ impl CPUInstruction for INC8 {
read_8bit_from_address(registers, bus, self.addressing_mode),
) as u8;
write_8bit_to_address(registers, bus, self.addressing_mode, result);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -62,7 +62,7 @@ impl CPUInstruction for INC16 {
read_16bit_from_address(registers, bus, self.addressing_mode),
) as u16;
write_16bit_to_address(registers, bus, self.addressing_mode, result);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_inc_dec(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, dec_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "INX";
static INSTR_NAME: &str = "INX";
pub struct INX {}

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@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, dec_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "INY";
static INSTR_NAME: &str = "INY";
pub struct INY {}

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@@ -6,7 +6,7 @@ use super::CPUInstruction;
use super::decoder_common;
use crate::cpu::cycles;
static INSTR_NAME: &'static str = "JMP";
static INSTR_NAME: &str = "JMP";
pub struct JMP {
pub addressing_mode: AddressingMode,
@@ -14,12 +14,8 @@ pub struct JMP {
impl CPUInstruction for JMP {
fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
let effective_address = get_effective_address(&registers, bus, self.addressing_mode);
let is_long = match self.addressing_mode {
AddressingMode::AbsoluteLong |
AddressingMode::AbsoluteIndirectLong => true,
_ => false,
};
let effective_address = get_effective_address(registers, bus, self.addressing_mode);
let is_long = matches!(self.addressing_mode, AddressingMode::AbsoluteLong | AddressingMode::AbsoluteIndirectLong);
registers.pc = effective_address as u16;
if is_long {
registers.pbr = (effective_address >> 16) as u8;

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@@ -6,7 +6,7 @@ use super::{CPUInstruction, push_common};
use super::decoder_common;
use crate::cpu::cycles;
static INSTR_NAME: &'static str = "JSR";
static INSTR_NAME: &str = "JSR";
pub struct JSR {
pub addressing_mode: AddressingMode,
@@ -15,11 +15,7 @@ pub struct JSR {
impl CPUInstruction for JSR {
fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
let effective_address = get_effective_address(registers, bus, self.addressing_mode);
let is_long = match self.addressing_mode {
AddressingMode::AbsoluteLong |
AddressingMode::AbsoluteIndirectLong => true,
_ => false,
};
let is_long = matches!(self.addressing_mode, AddressingMode::AbsoluteLong | AddressingMode::AbsoluteIndirectLong);
// We need to push the *next* instruction onto the stack
let (bytes, cycles) = cycles::increment_cycles_jsr(self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;

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@@ -7,7 +7,7 @@ use super::read_write_common::{read_8bit_from_address, read_16bit_from_address};
use super::{CPUInstruction, bit_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "LDA";
static INSTR_NAME: &str = "LDA";
pub struct LDA {
pub addressing_mode: AddressingMode,
@@ -47,7 +47,7 @@ impl CPUInstruction for LDA8 {
]);
registers.set_low_a(value);
bit_common::do_bit(registers, registers.a as u8, value, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_lda(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_lda(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -68,7 +68,7 @@ impl CPUInstruction for LDA16 {
Flags::Negative(value >> 15 == 1),
Flags::Zero(value == 0),
]);
let (bytes, cycles) = cycles::increment_cycles_lda(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_lda(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

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@@ -7,7 +7,7 @@ use super::read_write_common::{read_8bit_from_address, read_16bit_from_address};
use super::{CPUInstruction, bit_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "LDX";
static INSTR_NAME: &str = "LDX";
pub struct LDX {
pub addressing_mode: AddressingMode,
@@ -47,7 +47,7 @@ impl CPUInstruction for LDX8 {
]);
registers.set_low_x(value);
bit_common::do_bit(registers, registers.x as u8, value, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_ld_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_ld_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -68,7 +68,7 @@ impl CPUInstruction for LDX16 {
Flags::Negative(value >> 15 == 1),
Flags::Zero(value == 0),
]);
let (bytes, cycles) = cycles::increment_cycles_ld_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_ld_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

View File

@@ -7,7 +7,7 @@ use super::read_write_common::{read_8bit_from_address, read_16bit_from_address};
use super::{CPUInstruction, bit_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "LDY";
static INSTR_NAME: &str = "LDY";
pub struct LDY {
pub addressing_mode: AddressingMode,
@@ -47,7 +47,7 @@ impl CPUInstruction for LDY8 {
]);
registers.set_low_y(value);
bit_common::do_bit(registers, registers.y as u8, value, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_ld_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_ld_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -68,7 +68,7 @@ impl CPUInstruction for LDY16 {
Flags::Negative(value >> 15 == 1),
Flags::Zero(value == 0),
]);
let (bytes, cycles) = cycles::increment_cycles_ld_index(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_ld_index(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{write_8bit_to_address, read_8bit_from_address, read_16bit_from_address, write_16bit_to_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "LSR";
static INSTR_NAME: &str = "LSR";
pub struct LSR {
pub addressing_mode: AddressingMode,
@@ -40,7 +40,7 @@ impl CPUInstruction for LSR8 {
let (result, affected_flags) = alu::lsr(read_8bit_from_address(registers, bus, self.addressing_mode));
write_8bit_to_address(registers, bus, self.addressing_mode, result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_shift(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_shift(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -58,7 +58,7 @@ impl CPUInstruction for LSR16 {
let (result, affected_flags) = alu::lsr(read_16bit_from_address(registers, bus, self.addressing_mode));
write_16bit_to_address(registers, bus, self.addressing_mode, result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_shift(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_shift(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

View File

@@ -3,7 +3,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::{CPUInstruction, move_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "MVN";
static INSTR_NAME: &str = "MVN";
pub struct MVN {}
@@ -16,13 +16,3 @@ impl CPUInstruction for MVN {
decoder_common::mnemonic_move(opcode, INSTR_NAME, registers, bus)
}
}
#[cfg(test)]
mod cpu_instructions_tests {
use super::*;
#[test]
fn test() {
}
}

View File

@@ -3,7 +3,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::{CPUInstruction, move_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "MVP";
static INSTR_NAME: &str = "MVP";
pub struct MVP {}
@@ -16,13 +16,3 @@ impl CPUInstruction for MVP {
decoder_common::mnemonic_move(opcode, INSTR_NAME, registers, bus)
}
}
#[cfg(test)]
mod cpu_instructions_tests {
use super::*;
#[test]
fn test() {
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "NOP";
static INSTR_NAME: &str = "NOP";
pub struct NOP {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16bit_from_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "ORA";
static INSTR_NAME: &str = "ORA";
pub struct ORA {
pub addressing_mode: AddressingMode,

View File

@@ -6,7 +6,7 @@ use super::read_write_common::get_effective_address;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PEA";
static INSTR_NAME: &str = "PEA";
pub struct PEA {}

View File

@@ -6,7 +6,7 @@ use super::read_write_common::get_effective_address;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PEI";
static INSTR_NAME: &str = "PEI";
pub struct PEI {}

View File

@@ -6,7 +6,7 @@ use super::read_write_common::get_effective_address;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PER";
static INSTR_NAME: &str = "PER";
pub struct PER {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PHA";
static INSTR_NAME: &str = "PHA";
pub struct PHA {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PHB";
static INSTR_NAME: &str = "PHB";
pub struct PHB {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PHD";
static INSTR_NAME: &str = "PHD";
pub struct PHD {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PHK";
static INSTR_NAME: &str = "PHK";
pub struct PHK {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PHP";
static INSTR_NAME: &str = "PHP";
pub struct PHP {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PHX";
static INSTR_NAME: &str = "PHX";
pub struct PHX {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, push_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PHY";
static INSTR_NAME: &str = "PHY";
pub struct PHY {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PLA";
static INSTR_NAME: &str = "PLA";
pub struct PLA {}
@@ -49,8 +49,8 @@ mod cpu_instructions_tests {
assert_eq!(registers.a, 0x1234);
assert_eq!(registers.sp, 0x1FC);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.get_negative_flag(), false);
assert_eq!(registers.get_zero_flag(), false);
assert!(!registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.cycles, 5);
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PLB";
static INSTR_NAME: &str = "PLB";
pub struct PLB {}
@@ -40,8 +40,8 @@ mod cpu_instructions_tests {
assert_eq!(registers.dbr, 0x12);
assert_eq!(registers.sp, 0x1FC);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.get_negative_flag(), false);
assert_eq!(registers.get_zero_flag(), false);
assert!(!registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.cycles, 4);
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PLD";
static INSTR_NAME: &str = "PLD";
pub struct PLD {}
@@ -42,8 +42,8 @@ mod cpu_instructions_tests {
assert_eq!(registers.d, 0x1234);
assert_eq!(registers.sp, 0x1FC);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.get_negative_flag(), false);
assert_eq!(registers.get_zero_flag(), false);
assert!(!registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.cycles, 5);
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PLP";
static INSTR_NAME: &str = "PLP";
pub struct PLP {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PLX";
static INSTR_NAME: &str = "PLX";
pub struct PLX {}
@@ -49,8 +49,8 @@ mod cpu_instructions_tests {
assert_eq!(registers.x, 0x1234);
assert_eq!(registers.sp, 0x1FC);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.get_negative_flag(), false);
assert_eq!(registers.get_zero_flag(), false);
assert!(!registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.cycles, 5);
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "PLY";
static INSTR_NAME: &str = "PLY";
pub struct PLY {}
@@ -49,8 +49,8 @@ mod cpu_instructions_tests {
assert_eq!(registers.y, 0x1234);
assert_eq!(registers.sp, 0x1FC);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.get_negative_flag(), false);
assert_eq!(registers.get_zero_flag(), false);
assert!(!registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.cycles, 5);
}
}

View File

@@ -13,7 +13,7 @@ pub fn do_pull(registers: &mut Registers, bus: &mut Bus, count: usize) -> Vec<u8
bytes.push(byte);
}
registers.set_zero_flag(is_zero);
if bytes.len() > 0 {
if !bytes.is_empty() {
// Low byte is pulled first, so we need to check
// for the last byte that we pull
registers.set_negative_flag((bytes[bytes.len() - 1] >> 7) == 1);

View File

@@ -1,25 +1,28 @@
use crate::{cpu::{registers::Registers, bus::Bus}, utils::addressing::AddressingMode};
use crate::{cpu::{registers::Registers, bus::Bus}, utils::addressing::{AddressingMode, ResolveAddressParams}};
pub fn get_effective_address(registers: &Registers, bus: &mut Bus, addressing_mode: AddressingMode) -> u32 {
addressing_mode.effective_address(
bus,
registers.get_pc_address(),
registers.d,
registers.sp,
registers.x, registers.y,
ResolveAddressParams {
pc_addr: registers.get_pc_address(),
direct_page_register: registers.d,
stack_pointer: registers.sp,
x: registers.x, y: registers.y,
}
)
}
pub fn read_8bit_from_address(registers: &Registers, bus: &mut Bus, addressing_mode: AddressingMode) -> u8 {
match addressing_mode {
AddressingMode::Accumulator => registers.a as u8,
_ => addressing_mode.value_8bit(
_ => addressing_mode.read_8bit(
ResolveAddressParams {
pc_addr: registers.get_pc_address(),
direct_page_register: registers.d,
stack_pointer: registers.sp,
x: registers.x, y: registers.y,
},
bus,
registers.get_pc_address(),
registers.d,
registers.sp,
registers.x,
registers.y,
)
}
}
@@ -27,13 +30,14 @@ pub fn read_8bit_from_address(registers: &Registers, bus: &mut Bus, addressing_m
pub fn read_16bit_from_address(registers: &Registers, bus: &mut Bus, addressing_mode: AddressingMode) -> u16 {
match addressing_mode {
AddressingMode::Accumulator => registers.a,
_ => addressing_mode.value_16bit(
_ => addressing_mode.read_16bit(
ResolveAddressParams {
pc_addr: registers.get_pc_address(),
direct_page_register: registers.d,
stack_pointer: registers.sp,
x: registers.x, y: registers.y,
},
bus,
registers.get_pc_address(),
registers.d,
registers.sp,
registers.x,
registers.y,
)
}
}
@@ -41,12 +45,14 @@ pub fn read_16bit_from_address(registers: &Registers, bus: &mut Bus, addressing_
pub fn write_8bit_to_address(registers: &mut Registers, bus: &mut Bus, addressing_mode: AddressingMode, value: u8) {
match addressing_mode {
AddressingMode::Accumulator => registers.set_low_a(value),
_ => addressing_mode.store_8bit(
_ => addressing_mode.write_8bit(
ResolveAddressParams {
pc_addr: registers.get_pc_address(),
direct_page_register: registers.d,
stack_pointer: registers.sp,
x: registers.x, y: registers.y,
},
bus,
registers.get_pc_address(),
registers.d,
registers.sp,
registers.x, registers.y,
value,
),
};
@@ -55,12 +61,14 @@ pub fn write_8bit_to_address(registers: &mut Registers, bus: &mut Bus, addressin
pub fn write_16bit_to_address(registers: &mut Registers, bus: &mut Bus, addressing_mode: AddressingMode, value: u16) {
match addressing_mode {
AddressingMode::Accumulator => registers.a = value,
_ => addressing_mode.store_16bit(
_ => addressing_mode.write_16bit(
ResolveAddressParams {
pc_addr: registers.get_pc_address(),
direct_page_register: registers.d,
stack_pointer: registers.sp,
x: registers.x, y: registers.y,
},
bus,
registers.get_pc_address(),
registers.d,
registers.sp,
registers.x, registers.y,
value,
),
};

View File

@@ -6,7 +6,7 @@ use super::read_write_common::read_8bit_from_address;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "REP";
static INSTR_NAME: &str = "REP";
pub struct REP {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{read_8bit_from_address, write_8bit_to_address, read_16bit_from_address, write_16bit_to_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "ROL";
static INSTR_NAME: &str = "ROL";
pub struct ROL {
pub addressing_mode: AddressingMode,
@@ -84,8 +84,8 @@ mod cpu_instructions_tests {
registers.pc = 0x0000;
let instruction = ROL8{addressing_mode: AddressingMode::Accumulator};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_negative_flag(), true);
assert_eq!(registers.get_zero_flag(), false);
assert!(registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.a, 0b1000_0000);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);
@@ -101,8 +101,8 @@ mod cpu_instructions_tests {
registers.pc = 0x0000;
let instruction = ROL16{addressing_mode: AddressingMode::Accumulator};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_negative_flag(), true);
assert_eq!(registers.get_zero_flag(), false);
assert!(registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.a, 0b10000000_00000000);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 4);

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{read_8bit_from_address, write_8bit_to_address, read_16bit_from_address, write_16bit_to_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "ROR";
static INSTR_NAME: &str = "ROR";
pub struct ROR {
pub addressing_mode: AddressingMode,
@@ -85,8 +85,8 @@ mod cpu_instructions_tests {
registers.pc = 0x0000;
let instruction = ROR8{addressing_mode: AddressingMode::Accumulator};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_carry_flag(), false);
assert_eq!(registers.get_zero_flag(), false);
assert!(!registers.get_carry_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.a, 0b1000_0000);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);
@@ -103,8 +103,8 @@ mod cpu_instructions_tests {
registers.pc = 0x0000;
let instruction = ROR16{addressing_mode: AddressingMode::Accumulator};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_negative_flag(), true);
assert_eq!(registers.get_zero_flag(), false);
assert!(registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.a, 0b10000000_00000000);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 4);

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "RTI";
static INSTR_NAME: &str = "RTI";
pub struct RTI {}
@@ -24,13 +24,3 @@ impl CPUInstruction for RTI {
decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
}
}
#[cfg(test)]
mod cpu_instructions_tests {
use super::*;
#[test]
fn test() {
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "RTL";
static INSTR_NAME: &str = "RTL";
pub struct RTL {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, pull_common};
use super::decoder_common;
static INSTR_NAME: &'static str = "RTS";
static INSTR_NAME: &str = "RTS";
pub struct RTS {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::{CPUInstruction, read_write_common::{read_8bit_from_address, read_16bit_from_address}};
use super::decoder_common;
static INSTR_NAME: &'static str = "SBC";
static INSTR_NAME: &str = "SBC";
pub struct SBC {
pub addressing_mode: AddressingMode,
@@ -51,7 +51,7 @@ impl CPUInstruction for SBC8BIN {
);
registers.set_low_a(result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -73,7 +73,7 @@ impl CPUInstruction for SBC16BIN {
);
registers.a = result;
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -95,7 +95,7 @@ impl CPUInstruction for SBC8BCD {
);
registers.set_low_a(result);
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}
@@ -117,7 +117,7 @@ impl CPUInstruction for SBC16BCD {
);
registers.a = result;
registers.set_flags(&affected_flags);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(&registers, self.addressing_mode);
let (bytes, cycles) = cycles::increment_cycles_arithmetic(registers, self.addressing_mode);
registers.increment_pc(bytes); registers.cycles += cycles;
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "SEC";
static INSTR_NAME: &str = "SEC";
pub struct SEC {}
@@ -33,7 +33,7 @@ mod cpu_instructions_tests {
registers.set_carry_flag(false);
let instruction = SEC{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_carry_flag(), true);
assert!(registers.get_carry_flag());
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "SED";
static INSTR_NAME: &str = "SED";
pub struct SED {}
@@ -33,7 +33,7 @@ mod cpu_instructions_tests {
registers.set_decimal_mode_flag(false);
let instruction = SED{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_decimal_mode_flag(), true);
assert!(registers.get_decimal_mode_flag());
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "SEI";
static INSTR_NAME: &str = "SEI";
pub struct SEI {}
@@ -33,7 +33,7 @@ mod cpu_instructions_tests {
registers.set_irq_disable_flag(false);
let instruction = SEI{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_irq_disable_flag(), true);
assert!(registers.get_irq_disable_flag());
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);
}

View File

@@ -6,7 +6,7 @@ use super::read_write_common::read_8bit_from_address;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "SEP";
static INSTR_NAME: &str = "SEP";
pub struct SEP {}

View File

@@ -6,7 +6,7 @@ use super::read_write_common::{write_8bit_to_address, write_16bit_to_address};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "STA";
static INSTR_NAME: &str = "STA";
pub struct STA {
pub addressing_mode: AddressingMode,

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "STP";
static INSTR_NAME: &str = "STP";
pub struct STP {}
@@ -34,7 +34,7 @@ mod cpu_instructions_tests {
let instruction = STP{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.is_cpu_stopped, true);
assert!(registers.is_cpu_stopped);
assert_eq!(registers.cycles, 3);
}
}

View File

@@ -6,7 +6,7 @@ use super::read_write_common::{write_8bit_to_address, write_16bit_to_address};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "STX";
static INSTR_NAME: &str = "STX";
pub struct STX {
pub addressing_mode: AddressingMode,

View File

@@ -6,7 +6,7 @@ use super::read_write_common::{write_8bit_to_address, write_16bit_to_address};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "STY";
static INSTR_NAME: &str = "STY";
pub struct STY {
pub addressing_mode: AddressingMode,

View File

@@ -6,7 +6,7 @@ use super::read_write_common::{write_8bit_to_address, write_16bit_to_address};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "STZ";
static INSTR_NAME: &str = "STZ";
pub struct STZ {
pub addressing_mode: AddressingMode,

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TAX";
static INSTR_NAME: &str = "TAX";
pub struct TAX {}
@@ -78,8 +78,8 @@ mod cpu_instructions_tests {
registers.set_16bit_index(false);
let instruction = TAX8{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_negative_flag(), true);
assert_eq!(registers.get_zero_flag(), false);
assert!(registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.x, 0x00FF);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);
@@ -97,8 +97,8 @@ mod cpu_instructions_tests {
registers.set_16bit_index(true);
let instruction = TAX16{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_negative_flag(), true);
assert_eq!(registers.get_zero_flag(), false);
assert!(registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.x, 0xF0F0);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TAY";
static INSTR_NAME: &str = "TAY";
pub struct TAY {}
@@ -79,8 +79,8 @@ mod cpu_instructions_tests {
registers.set_16bit_index(false);
let instruction = TAY8{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_negative_flag(), true);
assert_eq!(registers.get_zero_flag(), false);
assert!(registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.y, 0x00FF);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);
@@ -98,8 +98,8 @@ mod cpu_instructions_tests {
registers.set_16bit_index(true);
let instruction = TAY16{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.get_negative_flag(), true);
assert_eq!(registers.get_zero_flag(), false);
assert!(registers.get_negative_flag());
assert!(!registers.get_zero_flag());
assert_eq!(registers.y, 0xF0F0);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.cycles, 2);

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TCD";
static INSTR_NAME: &str = "TCD";
pub struct TCD {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TCS";
static INSTR_NAME: &str = "TCS";
pub struct TCS {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TDC";
static INSTR_NAME: &str = "TDC";
pub struct TDC {}

View File

@@ -6,7 +6,7 @@ use super::read_write_common::{read_8bit_from_address, write_8bit_to_address, re
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TRB";
static INSTR_NAME: &str = "TRB";
pub struct TRB {
pub addressing_mode: AddressingMode,
@@ -70,13 +70,3 @@ impl CPUInstruction for TRB16 {
decoder_common::mnemonic_arithmetic(true, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
}
}
#[cfg(test)]
mod cpu_instructions_tests {
use super::*;
#[test]
fn test() {
}
}

View File

@@ -6,7 +6,7 @@ use super::read_write_common::{read_8bit_from_address, write_8bit_to_address, re
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TSB";
static INSTR_NAME: &str = "TSB";
pub struct TSB {
pub addressing_mode: AddressingMode,
@@ -68,13 +68,3 @@ impl CPUInstruction for TSB16 {
decoder_common::mnemonic_arithmetic(true, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
}
}
#[cfg(test)]
mod cpu_instructions_tests {
use super::*;
#[test]
fn test() {
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TSC";
static INSTR_NAME: &str = "TSC";
pub struct TSC {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TSX";
static INSTR_NAME: &str = "TSX";
pub struct TSX {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TXA";
static INSTR_NAME: &str = "TXA";
pub struct TXA {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TXS";
static INSTR_NAME: &str = "TXS";
pub struct TXS {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TXY";
static INSTR_NAME: &str = "TXY";
pub struct TXY {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TYA";
static INSTR_NAME: &str = "TYA";
pub struct TYA {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "TYX";
static INSTR_NAME: &str = "TYX";
pub struct TYX {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "WAI";
static INSTR_NAME: &str = "WAI";
pub struct WAI {}
@@ -34,7 +34,7 @@ mod cpu_instructions_tests {
let instruction = WAI{};
instruction.execute(&mut registers, &mut bus);
assert_eq!(registers.pc, 0x0001);
assert_eq!(registers.is_cpu_waiting_interrupt, true);
assert!(registers.is_cpu_waiting_interrupt);
assert_eq!(registers.cycles, 3);
}
}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "WDM";
static INSTR_NAME: &str = "WDM";
pub struct WDM {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "XBA";
static INSTR_NAME: &str = "XBA";
pub struct XBA {}

View File

@@ -4,7 +4,7 @@ use crate::cpu::cycles;
use super::CPUInstruction;
use super::decoder_common;
static INSTR_NAME: &'static str = "XCE";
static INSTR_NAME: &str = "XCE";
pub struct XCE {}

View File

@@ -39,7 +39,7 @@ impl CPU {
self.registers.increment_pc(bytes); self.registers.cycles += cycles;
return false;
}
return true;
true
}
pub fn tick(&mut self, bus: &mut Bus) {
@@ -51,3 +51,9 @@ impl CPU {
instruction.execute(&mut self.registers, bus);
}
}
impl Default for CPU {
fn default() -> Self {
Self::new()
}
}

View File

@@ -45,7 +45,7 @@ impl InternalRegisters {
pub fn write(&mut self, address: u16, value: u8, dma: &mut dma::DMA) {
self._write(address, value);
match address {
#[allow(clippy::single_match)] match address {
dma::MDMAEN => dma.prepare_dma_transfer(value),
_ => {},
}
@@ -53,8 +53,7 @@ impl InternalRegisters {
fn read_vblank_nmi(&self, ppu_registers: &PPURegisters) -> u8 {
let byte = self._read(RDNMI);
let result = (byte & 0x7F) | ((ppu_registers.vblank_nmi as u8) << 7);
result
(byte & 0x7F) | ((ppu_registers.vblank_nmi as u8) << 7)
}
fn read_vblank_nmi_mut(&self, ppu_registers: &mut PPURegisters) -> u8 {
@@ -66,11 +65,17 @@ impl InternalRegisters {
}
}
impl Default for InternalRegisters {
fn default() -> Self {
Self::new()
}
}
#[cfg(test)]
mod ppu_general_test {
use super::*;
use crate::ppu::ppu::PPU;
use crate::ppu::interface::PPU;
#[test]
fn test_read_vblank_nmi() {
@@ -78,13 +83,13 @@ mod ppu_general_test {
let mut ppu = PPU::new();
ppu.registers.h_count = 20;
ppu.dot_cycle();
assert_eq!(registers.read_vblank_nmi(&mut ppu.registers), 0x00);
assert_eq!(registers.read_vblank_nmi(&ppu.registers), 0x00);
ppu.registers.h_count = 339;
ppu.registers.v_count = 224;
ppu.dot_cycle();
assert_eq!(registers.read_vblank_nmi_mut(&mut ppu.registers), 0x80);
// vblank bit is reset after read
ppu.dot_cycle();
assert_eq!(registers.read_vblank_nmi(&mut ppu.registers), 0x00);
assert_eq!(registers.read_vblank_nmi(&ppu.registers), 0x00);
}
}

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