REP instruction

This commit is contained in:
2022-11-30 20:55:04 -05:00
parent a8844a1ae1
commit 4d190e9523
2 changed files with 40 additions and 0 deletions
+20
View File
@@ -738,6 +738,11 @@ impl CPU {
self.increment_cycles_pl_index();
}
fn rep(&mut self, bus: &Bus) {
self.registers.p = self.get_8bit_from_address(bus, AddressingMode::Immediate);
self.increment_cycles_rep();
}
pub fn execute_opcode(&mut self, opcode: u8, bus: &mut Bus) {
type A = AddressingMode;
type I = IndexRegister;
@@ -992,6 +997,8 @@ impl CPU {
0xFA => self.plx(bus),
// PLY
0x7A => self.ply(bus),
// REP
0xC2 => self.rep(bus),
_ => println!("Invalid opcode: {:02X}", opcode),
}
}
@@ -2073,4 +2080,17 @@ mod cpu_instructions_tests {
assert_eq!(cpu.registers.get_zero_flag(), false);
assert_eq!(cpu.cycles, 5);
}
#[test]
fn test_rep() {
let mut cpu = CPU::new();
let mut bus = Bus::new();
cpu.registers.pc = 0x0000;
cpu.registers.p = 0x00;
bus.write(0x0001, 0xFF);
cpu.rep(&mut bus);
assert_eq!(cpu.registers.p, 0xFF);
assert_eq!(cpu.registers.pc, 0x0002);
assert_eq!(cpu.cycles, 3);
}
}
+20
View File
@@ -9,9 +9,12 @@ pub trait SnesNum: Copy + Clone + Sized + Eq + PartialEq {
fn lsr(&self) -> Self;
fn xor(&self, v: Self) -> Self;
fn ora(&self, v: Self) -> Self;
fn rol(&self, carry: bool) -> Self;
fn ror(&self, carry: bool) -> Self;
fn is_negative(&self) -> bool;
fn is_zero(&self) -> bool;
fn next_to_highest_bit(&self) -> bool;
fn lowest_bit(&self) -> bool;
fn to_u32(&self) -> u32;
fn from_u32(v: u32) -> Self;
fn invert(&self) -> Self;
@@ -82,6 +85,19 @@ macro_rules! define_impl {
(* self) | v
}
fn rol(&self, carry: bool) -> $t {
((* self) << 1) | (carry as $t)
}
fn ror(&self, carry: bool) -> $t {
let mut result = ((* self) >> 1);
if carry {
result = result |
((<$t>::MAX) & !(<$t>::MAX >> 1))
}
result
}
fn is_negative(&self) -> bool {
(*self) & !(<$t>::MAX >> 1) != 0
}
@@ -90,6 +106,10 @@ macro_rules! define_impl {
(*self) == 0
}
fn lowest_bit(&self) -> bool {
(*self) & 1 == 1
}
fn next_to_highest_bit(&self) -> bool {
((*self) << 1) & !(<$t>::MAX >> 1) != 0
}