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https://github.com/FranLMSP/snes.git
synced 2026-01-01 07:21:35 -05:00
Minor fixes with addressing modes and ldy instr
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@@ -96,7 +96,7 @@ fn common_conditions(cpu_registers: &Registers, addressing_mode: AddressingMode,
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},
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// Add 1 byte if <index> = 0 (16-bit index registers)
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Condition::IndexIs16Bit => {
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if cpu_registers.is_16bit_index() {
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if addressing_mode == AddressingMode::Immediate && cpu_registers.is_16bit_index() {
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bytes += 1; cycles += 1;
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}
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},
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@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
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use crate::utils::addressing::AddressingMode;
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use super::read_write_common::{read_8bit_from_address, read_16bit_from_address};
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use super::{CPUInstruction, bit_common};
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use super::CPUInstruction;
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use super::decoder_common;
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static INSTR_NAME: &str = "LDA";
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@@ -41,12 +41,11 @@ pub struct LDA8 {
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impl CPUInstruction for LDA8 {
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fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
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let value = read_8bit_from_address(registers, bus, self.addressing_mode);
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registers.set_low_a(value);
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registers.set_flags(&[
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Flags::Negative(value >> 7 == 1),
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Flags::Zero(value == 0),
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]);
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registers.set_low_a(value);
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bit_common::do_bit(registers, registers.a as u8, value, self.addressing_mode);
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let (bytes, cycles) = cycles::increment_cycles_lda(registers, self.addressing_mode);
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registers.increment_pc(bytes); registers.cycles += cycles;
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}
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@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
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use crate::utils::addressing::AddressingMode;
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use super::read_write_common::{read_8bit_from_address, read_16bit_from_address};
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use super::{CPUInstruction, bit_common};
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use super::CPUInstruction;
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use super::decoder_common;
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static INSTR_NAME: &str = "LDX";
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@@ -41,12 +41,11 @@ pub struct LDX8 {
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impl CPUInstruction for LDX8 {
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fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
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let value = read_8bit_from_address(registers, bus, self.addressing_mode);
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registers.set_low_x(value);
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registers.set_flags(&[
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Flags::Negative(value >> 7 == 1),
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Flags::Zero(value == 0),
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]);
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registers.set_low_x(value);
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bit_common::do_bit(registers, registers.x as u8, value, self.addressing_mode);
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let (bytes, cycles) = cycles::increment_cycles_ld_index(registers, self.addressing_mode);
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registers.increment_pc(bytes); registers.cycles += cycles;
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}
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@@ -4,7 +4,7 @@ use crate::cpu::{bus::Bus, registers::Registers};
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use crate::utils::addressing::AddressingMode;
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use super::read_write_common::{read_8bit_from_address, read_16bit_from_address};
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use super::{CPUInstruction, bit_common};
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use super::CPUInstruction;
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use super::decoder_common;
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static INSTR_NAME: &str = "LDY";
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@@ -41,12 +41,11 @@ pub struct LDY8 {
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impl CPUInstruction for LDY8 {
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fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
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let value = read_8bit_from_address(registers, bus, self.addressing_mode);
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registers.set_low_y(value);
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registers.set_flags(&[
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Flags::Negative(value >> 7 == 1),
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Flags::Zero(value == 0),
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]);
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registers.set_low_y(value);
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bit_common::do_bit(registers, registers.y as u8, value, self.addressing_mode);
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let (bytes, cycles) = cycles::increment_cycles_ld_index(registers, self.addressing_mode);
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registers.increment_pc(bytes); registers.cycles += cycles;
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}
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@@ -178,8 +178,8 @@ pub fn map_opcode_to_instruction(opcode: u8) -> Box<dyn CPUInstruction> {
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0xA0 => Box::new(LDY{addressing_mode: A::Immediate}),
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0xAC => Box::new(LDY{addressing_mode: A::Absolute}),
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0xA4 => Box::new(LDY{addressing_mode: A::DirectPage}),
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0xB4 => Box::new(LDY{addressing_mode: A::AbsoluteIndexed(I::Y)}),
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0xBC => Box::new(LDY{addressing_mode: A::DirectPageIndexed(I::Y)}),
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0xBC => Box::new(LDY{addressing_mode: A::AbsoluteIndexed(I::X)}),
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0xB4 => Box::new(LDY{addressing_mode: A::DirectPageIndexed(I::X)}),
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// LSR
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0x4A => Box::new(LSR{addressing_mode: A::Accumulator}),
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0x4E => Box::new(LSR{addressing_mode: A::Absolute}),
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@@ -7,7 +7,7 @@ pub struct SpecialRAMCart {
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impl SpecialRAMCart {
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pub fn new() -> Self {
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Self {
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data: vec![0x00; 0x1000000],
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data: vec![0x00; 0x100000000],
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}
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}
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}
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@@ -21,7 +21,12 @@ pub fn immediate(pc_addr: u32) -> u32 {
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/// OPCODE addr
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pub fn absolute(bus: &mut Bus, pc_addr: u32, dbr: u8) -> u32 {
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let addr = (bus.read(pc_addr + 1) as u32) | ((bus.read(pc_addr + 2) as u32) << 8);
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let pbr = pc_addr & 0xFF0000;
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let bus_addr_1 = pbr | ((pc_addr as u16).wrapping_add(1) as u32);
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let bus_addr_2 = pbr | ((pc_addr as u16).wrapping_add(2) as u32);
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let addr =
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(bus.read(bus_addr_1) as u32) |
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((bus.read(bus_addr_2) as u32) << 8);
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((dbr as u32) << 16) | addr
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}
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@@ -49,7 +54,9 @@ pub fn absolute_indirect_long(bus: &mut Bus, pc_addr: u32, dbr: u8) -> u32 {
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/// OPCODE dp
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pub fn direct_page(bus: &mut Bus, pc_addr: u32, direct_page_register: u16) -> u32 {
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(bus.read(pc_addr + 1) as u16).wrapping_add(direct_page_register) as u32
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let pbr = pc_addr & 0xFF0000;
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let bus_addr = pbr | ((pc_addr as u16).wrapping_add(1) as u32);
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(bus.read(bus_addr) as u16).wrapping_add(direct_page_register) as u32
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}
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/// OPCODE (dp)
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@@ -142,7 +149,7 @@ impl Display for IndexRegister {
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}
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}
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#[derive(Copy, Clone)]
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#[derive(Copy, Clone, PartialEq)]
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pub enum AddressingMode {
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Accumulator,
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Immediate,
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