FranLMSP/rmg-001
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Author SHA1 Message Date
FranLMSP b0c07a5264 Refactor LCDControl 2021-10-31 07:32:19 -05:00
FranLMSP 5723c3b3b6 Fix interrupts, implement halt mode and fix IME 2021-10-31 07:25:47 -05:00
FranLMSP 61db367f31 Timer implement 2021-10-30 09:13:31 -05:00
FranLMSP abbd46ebed Refactor interrupt enum 2021-10-29 18:27:21 -05:00
FranLMSP 66731e1c8e Refactor interrupt implementation 2021-10-29 17:03:02 -05:00
FranLMSP c77bc9db70 Experimental interrupts 2021-10-29 15:40:47 -05:00
FranLMSP f90900a4c1 Enabling lcd and vblank flag registers 2021-10-28 22:13:23 -05:00
FranLMSP c401726da5 update readme 2021-10-28 19:42:15 -05:00
FranLMSP 7f9fdc9935 PPU timings 2021-10-28 19:38:30 -05:00
FranLMSP 6ad3f9f29b Experimental background rendering with scrolling 2021-10-28 12:58:03 -05:00
FranLMSP ce4afa96bf Rendering tiles with a temporally algorithm 2021-10-28 10:30:48 -05:00
FranLMSP 886fc3cd4a Rendering a basic window with pixels 2021-10-26 17:34:59 -05:00
FranLMSP 1444e8b63d Refactor address ranges 2021-10-22 15:32:12 -05:00
FranLMSP 88d5f08660 Getters and setters for LCD Status 2021-10-22 13:56:57 -05:00
FranLMSP bb471a7de7 Definitions for LCD status and control 2021-10-22 13:30:17 -05:00
FranLMSP d655442b9a Prevent crashing on debug 2021-10-22 09:56:54 -05:00
FranLMSP 707e9d76e1 Update to Rust version 2021 2021-10-21 11:10:19 -05:00
FranLMSP 3abdbbde85 Start modeling graphics 2021-10-21 11:06:25 -05:00
FranLMSP d2bf668bdc Reducing some warnings 2021-10-20 18:24:13 -05:00
FranLMSP 758772200f Some refactors on instructions 2021-10-20 18:16:45 -05:00
FranLMSP 09c9ef16aa Refactor parameter bytes 2021-10-20 18:03:59 -05:00
FranLMSP 72ad41f121 Implement cycle counting 2021-10-20 16:32:01 -05:00
FranLMSP aa60d8586f Update project name again 2021-10-20 14:33:11 -05:00
FranLMSP bdd2b4659a Test rom 10 2021-10-20 13:47:59 -05:00
FranLMSP b154b4a5cb Fix some LD and rotate instructions 2021-10-20 13:39:39 -05:00
FranLMSP 82fafad9cc Fix RST instruction 2021-10-20 12:29:55 -05:00
FranLMSP a4659dc147 Testing more roms 2021-10-19 22:36:10 -05:00
FranLMSP 0a1f075734 Fix ADC and SBC instructions 2021-10-19 21:55:35 -05:00
FranLMSP 39ea049fda Fix many signed ADD 2021-10-19 20:10:17 -05:00
FranLMSP fade566d12 Overflow bug 2021-10-19 14:34:23 -05:00
FranLMSP 3b81d34d71 More bugs on add instructions 2021-10-19 14:33:11 -05:00
FranLMSP 8b287c17c7 Fix ADD carry 2021-10-19 13:59:53 -05:00
FranLMSP 6b1d50ba76 Prevent panic on adding or sub with overflow on CPU 2021-10-19 13:17:14 -05:00
FranLMSP f928207a8d 0xF8 instruction 2021-10-19 11:04:52 -05:00
FranLMSP 76684cd523 Update readme 2021-10-19 10:46:40 -05:00
FranLMSP 520dbaeb17 Update project name 2021-10-19 10:44:12 -05:00
FranLMSP 5d710c3504 Update readme 2021-10-19 10:42:47 -05:00
FranLMSP b6b7e7bf73 Last interrupt instructions 2021-10-19 10:41:18 -05:00
FranLMSP ff9fd48190 SCF instruction 2021-10-19 10:33:43 -05:00
FranLMSP 08513ae110 CCF Instruction 2021-10-19 10:30:36 -05:00
FranLMSP ad5211d057 CPL Instruction 2021-10-19 10:24:54 -05:00
FranLMSP 7bdbfebd0e Trim some lines 2021-10-19 10:12:17 -05:00
FranLMSP 9013c09437 SET instruction 2021-10-19 10:06:22 -05:00
FranLMSP e4586db39a RES instruction 2021-10-19 10:02:43 -05:00
FranLMSP edc8429aa2 BIT instruction 2021-10-19 09:53:50 -05:00
FranLMSP a64d15c9ce SWAP instruction 2021-10-19 09:40:42 -05:00
FranLMSP d1029c1dc7 Uncommenting some asserts 2021-10-19 09:26:49 -05:00
FranLMSP 3f46ab4a54 Fix DAA instruction 2021-10-19 09:22:23 -05:00
FranLMSP f1a035d5ac WIP DAA instruction 2021-10-18 23:24:04 -05:00
FranLMSP b964992f8a Implement more JP instructions 2021-10-18 18:46:17 -05:00
FranLMSP eeeba76ebd ADD instruction bug 2021-10-18 18:18:57 -05:00
FranLMSP ac91f8f50d Fix INC and DEC 2021-10-18 17:27:46 -05:00
FranLMSP 199470cc70 RET instructions 2021-10-18 16:54:25 -05:00
FranLMSP 581e1c19d6 Bug on RET instruction 2021-10-18 13:18:15 -05:00
FranLMSP aded5fe534 ADC and SBC instructions (no tests) 2021-10-18 13:15:26 -05:00
FranLMSP 2b633c9ee0 RL and RR instructions bug 2021-10-18 12:45:16 -05:00
FranLMSP ca4a6c9f6a Bug RLA and RRA 2021-10-18 12:31:25 -05:00
FranLMSP 59acdd555e Fix SRL instruction 2021-10-18 12:03:24 -05:00
FranLMSP 9b08306c96 Temporally omitting tests for SLA and SRA 2021-10-18 10:57:06 -05:00
FranLMSP d093aa483d One more test with bus 2021-10-18 10:33:59 -05:00
FranLMSP aad827f05f RR instruction 2021-10-18 10:25:45 -05:00
FranLMSP 8d1a0f6f2f RL instruction 2021-10-18 10:13:23 -05:00
FranLMSP 9adf41ee47 16bit substraction is not really needed 2021-10-18 08:44:22 -05:00
FranLMSP 7c804029ad Some refactors 2021-10-18 08:28:19 -05:00
FranLMSP f148ee5ba6 Prefix CB RRC instruction 2021-10-17 21:45:55 -05:00
FranLMSP ec34a71fcf Mapping CB prefix instructions 2021-10-17 20:42:36 -05:00
FranLMSP 3897c3561e add and sub instructions 2021-10-17 19:14:41 -05:00
FranLMSP a8f00f46fd more CALL instructions 2021-10-17 13:12:04 -05:00
FranLMSP 31e0b2c79c Little refactor call instruction 2021-10-17 12:48:18 -05:00
FranLMSP ebadad803b Bug on LD instruction 2021-10-17 12:29:02 -05:00
FranLMSP e1d29d9530 Emulate Echo RAM 2021-10-17 12:02:33 -05:00
FranLMSP b3ba7b309e CP instruction 2021-10-17 10:55:16 -05:00
FranLMSP b098d28f0e AND, OR and XOR instructions 2021-10-16 22:38:13 -05:00
FranLMSP 12b43ee985 Fix PUSH instruction 2021-10-16 20:50:31 -05:00
FranLMSP 989971af8b Implement push and refactor pop 2021-10-16 19:41:07 -05:00
FranLMSP 4dbcb4cb6c Update readme 2021-10-16 16:33:48 -05:00
FranLMSP d24f048c86 Another LD instruction 2021-10-16 14:50:01 -05:00
FranLMSP f94314ad01 Fix some bugs and implement a way to compare the logs 2021-10-16 14:17:28 -05:00
FranLMSP 15e3d6685b Fix some bugs on instructions 2021-10-16 13:14:02 -05:00
FranLMSP afaecf597f Fix some tests, add a couple of new instructions and fix LD instruction bug 2021-10-15 20:59:35 -05:00
FranLMSP 9d8d05c660 Including more test roms and initializing the registers 2021-10-15 19:49:36 -05:00
FranLMSP f9d5cfaa02 Refactor 16bit bus read write 2021-10-15 19:18:00 -05:00
FranLMSP 891a72ad73 POP and RET instructions 2021-10-15 15:08:26 -05:00
FranLMSP 0a1edfa39e More tests for INC and DEC with 16bit registers 2021-10-15 13:44:05 -05:00
FranLMSP c55256a5b7 Refactor register bit length detection 2021-10-15 09:49:35 -05:00
FranLMSP dbe95bedf2 Increment and decrement instructions 2021-10-14 23:58:51 -05:00
FranLMSP 724cb27c49 Functions and tests for detecting half carry 2021-10-14 23:32:48 -05:00
FranLMSP b2190d1868 Refactor enums 2021-10-14 21:54:43 -05:00
FranLMSP 253da76fd5 CALL u16 and RST instructions 2021-10-14 17:07:51 -05:00
FranLMSP d26b77dc78 Some refactors 2021-10-14 16:13:28 -05:00
FranLMSP a5fad87319 RLCA, LD and DI instructions 2021-10-14 13:25:20 -05:00
FranLMSP bc3b25857b Little refactor 2021-10-14 08:38:57 -05:00
FranLMSP 92229e3d93 JP u16 instruction 2021-10-13 20:50:48 -05:00
FranLMSP 5d04b7c346 Modeling the Bus and writing first test for NOP instruction 2021-10-13 19:38:37 -05:00
FranLMSP 2afa2a1ff8 Memory maps 2021-10-13 12:56:00 -05:00
FranLMSP 1902884df9 Logic to load a rom file 2021-10-12 19:11:52 -05:00
FranLMSP 1e363187f1 Define test for CPU instructions (no tests yet) 2021-10-12 18:29:25 -05:00
FranLMSP f62926a869 Enum most opcode parameters (CB prefix remaining) 2021-10-12 18:06:07 -05:00
FranLMSP 9bf80459a7 Add illegal instruction 2021-10-12 12:52:04 -05:00
FranLMSP bbf6b19957 Mapping opcodes 2021-10-11 20:38:37 -05:00