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compute-background-framebuffer

cpu-interrupts

display-tv-output

fix-adc

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implement-egui

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more-ppu-rendering

refactor-cpu-instructions

refactor-cycle-increments

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• ab6c526892 CLC, CLD, CLI and CLV instructions FranLMSP 2022-11-24 23:23:18 -05:00
• 0ea8fdca2c BIT instruction FranLMSP 2022-11-24 23:10:02 -05:00
• e9f3cd24c7 Refactor affected flags on alu function FranLMSP 2022-11-23 23:05:00 -05:00
• fbee6fa8e9 set_flags function FranLMSP 2022-11-23 21:57:41 -05:00
• fa230e4a52 Refactor BCD operations FranLMSP 2022-11-23 21:07:57 -05:00
• d0e02cd9cd set overflow flag for adc and sbc FranLMSP 2022-11-21 21:51:13 -05:00
• cc9968dd93 Small refactor to cycles module FranLMSP 2022-11-21 19:06:26 -05:00
• 89a81917e0 Refactur alu tests FranLMSP 2022-11-21 18:50:35 -05:00
• 686069dd03 Refactor asl FranLMSP 2022-11-21 18:45:09 -05:00
• 7a17cb4038 Refactor and FranLMSP 2022-11-21 18:34:05 -05:00
• 992112229e refactor sbc_bin FranLMSP 2022-11-21 18:26:55 -05:00
• 6706daa872 Refactor adc_bin FranLMSP 2022-11-21 18:18:24 -05:00
• 20747f5fad ASL instruction FranLMSP 2022-11-20 23:19:39 -05:00
• f78883257a AND instructions FranLMSP 2022-11-20 20:55:23 -05:00
• 49bb3a04cc Refactor increment cycles function FranLMSP 2022-11-20 19:54:36 -05:00
• d00581011f condition for adding cycle to indexed addressing modes FranLMSP 2022-11-20 17:38:47 -05:00
• 9fc1fd66d0 update readme FranLMSP 2022-11-20 17:09:10 -05:00
• 794cbef477 Base byte and cycles calculation based on addressing mode FranLMSP 2022-11-20 17:07:21 -05:00
• 6178e223ba Merge branch 'main' of github.com:FranLMSP/snes FranLMSP 2022-11-20 12:19:27 -05:00
• 50ce162ea6 set_low_a function FranLMSP 2022-11-20 12:18:25 -05:00
• 4ddc3b3aa7 SBC opcodes FranLMSP 2022-11-20 12:10:17 -05:00
• f8a6872b8c Fix BCD substraction FranLMSP 2022-11-20 11:32:02 -05:00
• 8a1e04d32a Create LICENSE FranLMSP 2022-11-09 22:08:52 -05:00
• d90017111c WIP DEC functions FranLMSP 2022-11-09 21:06:09 -05:00
• c12d721da2 update readme FranLMSP 2022-10-13 12:23:43 -05:00
• 391e29c365 Fix bcd additions FranLMSP 2022-10-13 12:07:58 -05:00
• e1f9542cca Refactor opcode execution and adc instruction FranLMSP 2022-10-13 00:37:03 -05:00
• 6acf97c7bd Small refactor for match statement FranLMSP 2022-10-12 07:42:32 -05:00
• f6f2ebb8a8 Get value from address mode FranLMSP 2022-10-11 21:58:06 -05:00
• 94da58de32 Update readme FranLMSP 2022-10-10 22:17:07 -05:00
• 3dc25cf551 Address addressing modes FranLMSP 2022-10-10 22:13:26 -05:00
• c8a44116b8 readme draft FranLMSP 2022-10-10 22:13:12 -05:00
• 761303a237 BCD addition for 8 and 16 bits FranLMSP 2022-10-04 21:47:52 -05:00
• 54c0f6d738 Unit tests for adc8bcd FranLMSP 2022-09-25 18:29:15 -05:00
• a136136766 alu 8 and 16 bit bin add FranLMSP 2022-07-12 21:17:45 -05:00
• 66f9b5e62e Refactor CPU module FranLMSP 2022-07-06 21:00:17 -05:00
• 40ab4a8ec4 adc direct page indirect and indirect long FranLMSP 2022-07-06 20:21:21 -05:00
• 8460192ab3 adc direct page FranLMSP 2022-06-29 22:36:47 -05:00
• 96bf18df47 adc addr and adc long FranLMSP 2022-06-29 21:48:32 -05:00
• 52d63a7ae7 index register select flag FranLMSP 2022-06-29 19:33:25 -05:00
• f22328b678 read_immediate function FranLMSP 2022-06-29 19:21:31 -05:00
• 4c61fe9906 WIP Bus implementation FranLMSP 2022-06-27 22:17:14 -05:00
• c7a38ecc95 ADC function FranLMSP 2022-06-26 20:23:26 -05:00
• 4f802b33e2 First commit: flag registers and imgui example code (stolen from gh) FranLMSP 2022-06-26 17:49:35 -05:00