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31aa639a3c
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NOP
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2022-11-27 09:10:36 -05:00 |
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253201c6c5
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LSR instruction
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2022-11-27 09:08:44 -05:00 |
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9980ce2c9f
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INC, INX and INY instructions
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2022-11-26 22:23:20 -05:00 |
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53cb8b1d9e
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EOR
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2022-11-26 22:15:51 -05:00 |
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fdb324686a
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alu XOR
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2022-11-26 22:02:08 -05:00 |
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82f8676a39
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DEC, DEX and DEY instructions
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2022-11-26 21:51:51 -05:00 |
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b1b80e0c48
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Small refactor for CMP instructions
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2022-11-26 19:45:28 -05:00 |
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df6424a6c4
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CPX and CPY instructions
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2022-11-26 19:19:27 -05:00 |
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c37a4c3ba1
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cmp instruction
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2022-11-26 18:44:39 -05:00 |
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912099cf8d
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unimplemented brk instruction
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2022-11-25 21:56:46 -05:00 |
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e13b93d9e3
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Branch instructions
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2022-11-25 21:52:57 -05:00 |
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ab6c526892
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CLC, CLD, CLI and CLV instructions
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2022-11-24 23:23:18 -05:00 |
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0ea8fdca2c
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BIT instruction
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2022-11-24 23:10:02 -05:00 |
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e9f3cd24c7
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Refactor affected flags on alu function
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2022-11-23 23:05:00 -05:00 |
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fbee6fa8e9
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set_flags function
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2022-11-23 21:57:41 -05:00 |
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fa230e4a52
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Refactor BCD operations
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2022-11-23 21:07:57 -05:00 |
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d0e02cd9cd
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set overflow flag for adc and sbc
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2022-11-21 21:51:13 -05:00 |
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cc9968dd93
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Small refactor to cycles module
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2022-11-21 19:06:26 -05:00 |
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89a81917e0
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Refactur alu tests
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2022-11-21 18:53:58 -05:00 |
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686069dd03
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Refactor asl
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2022-11-21 18:45:09 -05:00 |
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7a17cb4038
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Refactor and
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2022-11-21 18:34:05 -05:00 |
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992112229e
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refactor sbc_bin
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2022-11-21 18:26:55 -05:00 |
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6706daa872
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Refactor adc_bin
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2022-11-21 18:18:24 -05:00 |
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20747f5fad
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ASL instruction
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2022-11-20 23:19:39 -05:00 |
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f78883257a
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AND instructions
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2022-11-20 20:55:23 -05:00 |
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49bb3a04cc
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Refactor increment cycles function
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2022-11-20 19:54:36 -05:00 |
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d00581011f
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condition for adding cycle to indexed addressing modes
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2022-11-20 17:38:47 -05:00 |
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9fc1fd66d0
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update readme
|
2022-11-20 17:09:10 -05:00 |
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794cbef477
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Base byte and cycles calculation based on addressing mode
|
2022-11-20 17:07:21 -05:00 |
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6178e223ba
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Merge branch 'main' of github.com:FranLMSP/snes
|
2022-11-20 12:19:27 -05:00 |
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50ce162ea6
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set_low_a function
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2022-11-20 12:18:25 -05:00 |
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4ddc3b3aa7
|
SBC opcodes
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2022-11-20 12:11:36 -05:00 |
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f8a6872b8c
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Fix BCD substraction
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2022-11-20 11:32:02 -05:00 |
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8a1e04d32a
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Create LICENSE
|
2022-11-09 22:08:52 -05:00 |
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d90017111c
|
WIP DEC functions
|
2022-11-09 21:06:09 -05:00 |
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c12d721da2
|
update readme
|
2022-10-13 12:23:43 -05:00 |
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391e29c365
|
Fix bcd additions
|
2022-10-13 12:15:22 -05:00 |
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e1f9542cca
|
Refactor opcode execution and adc instruction
|
2022-10-13 00:37:03 -05:00 |
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6acf97c7bd
|
Small refactor for match statement
|
2022-10-12 07:42:32 -05:00 |
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f6f2ebb8a8
|
Get value from address mode
|
2022-10-11 21:58:06 -05:00 |
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94da58de32
|
Update readme
|
2022-10-10 22:17:07 -05:00 |
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3dc25cf551
|
Address addressing modes
|
2022-10-10 22:13:26 -05:00 |
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c8a44116b8
|
readme draft
|
2022-10-10 22:13:12 -05:00 |
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761303a237
|
BCD addition for 8 and 16 bits
|
2022-10-04 21:47:52 -05:00 |
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54c0f6d738
|
Unit tests for adc8bcd
|
2022-09-25 18:30:53 -05:00 |
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a136136766
|
alu 8 and 16 bit bin add
|
2022-07-12 21:17:45 -05:00 |
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66f9b5e62e
|
Refactor CPU module
|
2022-07-06 21:00:17 -05:00 |
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40ab4a8ec4
|
adc direct page indirect and indirect long
|
2022-07-06 20:21:21 -05:00 |
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8460192ab3
|
adc direct page
|
2022-06-29 22:36:47 -05:00 |
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96bf18df47
|
adc addr and adc long
|
2022-06-29 21:49:05 -05:00 |
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