FranLMSP/snes
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Author SHA1 Message Date
FranLMSP cc9968dd93 Small refactor to cycles module 2022-11-21 19:06:26 -05:00
FranLMSP 89a81917e0 Refactur alu tests 2022-11-21 18:53:58 -05:00
FranLMSP 686069dd03 Refactor asl 2022-11-21 18:45:09 -05:00
FranLMSP 7a17cb4038 Refactor and 2022-11-21 18:34:05 -05:00
FranLMSP 992112229e refactor sbc_bin 2022-11-21 18:26:55 -05:00
FranLMSP 6706daa872 Refactor adc_bin 2022-11-21 18:18:24 -05:00
FranLMSP 20747f5fad ASL instruction 2022-11-20 23:19:39 -05:00
FranLMSP f78883257a AND instructions 2022-11-20 20:55:23 -05:00
FranLMSP 49bb3a04cc Refactor increment cycles function 2022-11-20 19:54:36 -05:00
FranLMSP d00581011f condition for adding cycle to indexed addressing modes 2022-11-20 17:38:47 -05:00
FranLMSP 9fc1fd66d0 update readme 2022-11-20 17:09:10 -05:00
FranLMSP 794cbef477 Base byte and cycles calculation based on addressing mode 2022-11-20 17:07:21 -05:00
FranLMSP 6178e223ba Merge branch 'main' of github.com:FranLMSP/snes 2022-11-20 12:19:27 -05:00
FranLMSP 50ce162ea6 set_low_a function 2022-11-20 12:18:25 -05:00
FranLMSP 4ddc3b3aa7 SBC opcodes 2022-11-20 12:11:36 -05:00
FranLMSP f8a6872b8c Fix BCD substraction 2022-11-20 11:32:02 -05:00
FranLMSP 8a1e04d32a Create LICENSE 2022-11-09 22:08:52 -05:00
FranLMSP d90017111c WIP DEC functions 2022-11-09 21:06:09 -05:00
FranLMSP c12d721da2 update readme 2022-10-13 12:23:43 -05:00
FranLMSP 391e29c365 Fix bcd additions 2022-10-13 12:15:22 -05:00
FranLMSP e1f9542cca Refactor opcode execution and adc instruction 2022-10-13 00:37:03 -05:00
FranLMSP 6acf97c7bd Small refactor for match statement 2022-10-12 07:42:32 -05:00
FranLMSP f6f2ebb8a8 Get value from address mode 2022-10-11 21:58:06 -05:00
FranLMSP 94da58de32 Update readme 2022-10-10 22:17:07 -05:00
FranLMSP 3dc25cf551 Address addressing modes 2022-10-10 22:13:26 -05:00
FranLMSP c8a44116b8 readme draft 2022-10-10 22:13:12 -05:00
FranLMSP 761303a237 BCD addition for 8 and 16 bits 2022-10-04 21:47:52 -05:00
FranLMSP 54c0f6d738 Unit tests for adc8bcd 2022-09-25 18:30:53 -05:00
FranLMSP a136136766 alu 8 and 16 bit bin add 2022-07-12 21:17:45 -05:00
FranLMSP 66f9b5e62e Refactor CPU module 2022-07-06 21:00:17 -05:00
FranLMSP 40ab4a8ec4 adc direct page indirect and indirect long 2022-07-06 20:21:21 -05:00
FranLMSP 8460192ab3 adc direct page 2022-06-29 22:36:47 -05:00
FranLMSP 96bf18df47 adc addr and adc long 2022-06-29 21:49:05 -05:00
FranLMSP 52d63a7ae7 index register select flag 2022-06-29 19:33:25 -05:00
FranLMSP f22328b678 read_immediate function 2022-06-29 19:21:31 -05:00
FranLMSP 4c61fe9906 WIP Bus implementation 2022-06-27 22:23:34 -05:00
FranLMSP c7a38ecc95 ADC function 2022-06-26 20:23:26 -05:00
FranLMSP 4f802b33e2 First commit: flag registers and imgui example code (stolen from gh) 2022-06-26 17:49:35 -05:00