From fa4fa2134bf0a7bf61f6c74a2775d8499dee641d Mon Sep 17 00:00:00 2001
From: Franco Colmenarez <info@francoacg.com>
Date: Wed, 27 Dec 2023 21:43:29 -0500
Subject: [PATCH] bit

---
 snes-core/src/cpu/instructionstemp/bit.rs     | 107 ++++++++++++++++++
 .../src/cpu/instructionstemp/bit_common.rs    |  14 +++
 snes-core/src/cpu/instructionstemp/mod.rs     |   2 +
 3 files changed, 123 insertions(+)
 create mode 100644 snes-core/src/cpu/instructionstemp/bit.rs
 create mode 100644 snes-core/src/cpu/instructionstemp/bit_common.rs

diff --git a/snes-core/src/cpu/instructionstemp/bit.rs b/snes-core/src/cpu/instructionstemp/bit.rs
new file mode 100644
index 0000000..454f1c7
--- /dev/null
+++ b/snes-core/src/cpu/instructionstemp/bit.rs
@@ -0,0 +1,107 @@
+use crate::{cpu::{bus::Bus, registers::Registers}, utils::addressing::AddressingMode};
+
+use crate::cpu::cycles;
+use super::{CPUInstruction, Decode, read_8bit_from_address, read_16bit_from_address, bit_common};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "BIT";
+
+pub struct BIT8 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for BIT8 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        bit_common::do_bit(
+            registers,
+            registers.a as u8,
+            read_8bit_from_address(registers, bus, self.addressing_mode),
+            self.addressing_mode,
+        );
+        let (bytes, cycles) = cycles::increment_cycles_bit(&registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for BIT8 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(false, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+pub struct BIT16 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for BIT16 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        bit_common::do_bit(
+            registers,
+            registers.a,
+            read_16bit_from_address(registers, bus, self.addressing_mode),
+            self.addressing_mode,
+        );
+        let (bytes, cycles) = cycles::increment_cycles_bit(&registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for BIT16 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(true, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test_8bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.emulation_mode = false;
+        registers.a   = 0b1111_0000;
+        registers.pbr = 0x00;
+        registers.pc  = 0x0000;
+        registers.p   = 0x00;
+        bus.write(0x000001, 0b0000_1111);
+        registers.set_16bit_mode(false);
+        let instruction = BIT8{addressing_mode: AddressingMode::Immediate};
+        instruction.execute(&mut registers, &mut bus);
+        // Check that it only affects the zero flag on immediate mode
+        assert_eq!(registers.a, 0b1111_0000); // Check that A is not altered
+        assert_eq!(registers.p, 0b0010_0010); // Only zero flag was altered (bit 6 is memory select mode)
+        assert_eq!(registers.pc, 0x02);
+        assert_eq!(registers.cycles, 2);
+        assert!(registers.get_zero_flag());
+    }
+
+    #[test]
+    fn test_16bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.emulation_mode = false;
+        registers.a   = 0b00110000_00000000;
+        registers.pbr = 0x00;
+        registers.pc  = 0x0000;
+        registers.p   = 0x00;
+        registers.cycles        = 0;
+        // Write absolute address
+        bus.write(0x000001, 0x04);
+        bus.write(0x000002, 0x00);
+        // Write effective value of address
+        bus.write(0x000004, 0x00);
+        bus.write(0x000005, 0b1100_0000);
+        registers.set_16bit_mode(true);
+        let instruction = BIT16{addressing_mode: AddressingMode::Immediate};
+        instruction.execute(&mut registers, &mut bus);
+        // Check that it only affects the zero flag on immediate mode
+        assert_eq!(registers.a, 0b00110000_00000000); // Check that A is not altered
+        assert_eq!(registers.p, 0b0000_0010);
+        assert_eq!(registers.pc, 0x03);
+        assert_eq!(registers.cycles, 3);
+        assert!(registers.get_zero_flag());
+    }
+}
diff --git a/snes-core/src/cpu/instructionstemp/bit_common.rs b/snes-core/src/cpu/instructionstemp/bit_common.rs
new file mode 100644
index 0000000..5043a28
--- /dev/null
+++ b/snes-core/src/cpu/instructionstemp/bit_common.rs
@@ -0,0 +1,14 @@
+use crate::{cpu::registers::Registers, utils::{num_trait::SnesNum, addressing::AddressingMode, alu}};
+
+pub fn do_bit<T: SnesNum>(registers: &mut Registers, accumulator: T, value: T, addressing_mode: AddressingMode) {
+    let (result, _) = alu::and(accumulator, value);
+    // Immediate addressing affects only the zero flag
+    match addressing_mode {
+        AddressingMode::Immediate => registers.set_zero_flag(result.is_zero()),
+        _ => {
+            registers.set_zero_flag(result.is_zero());
+            registers.set_negative_flag(value.is_negative());
+            registers.set_overflow_flag(value.next_to_highest_bit());
+        }
+    };
+}
diff --git a/snes-core/src/cpu/instructionstemp/mod.rs b/snes-core/src/cpu/instructionstemp/mod.rs
index 49224c6..117f7bd 100644
--- a/snes-core/src/cpu/instructionstemp/mod.rs
+++ b/snes-core/src/cpu/instructionstemp/mod.rs
@@ -16,6 +16,8 @@ pub mod brk;
 pub mod brl;
 pub mod bvc;
 pub mod bvs;
+pub mod bit;
+pub mod bit_common;
 pub mod decoder_common;
 pub mod branch_common;
 pub mod push_common;