mirror of
https://github.com/FranLMSP/snes.git
synced 2026-08-03 08:30:01 -04:00
define all ppu registers
This commit is contained in:
@@ -1,10 +1,10 @@
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use crate::ppu::registers::PPURegisters;
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use crate::ppu::registers::{
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RDNMI
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};
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pub const INTERNAL_REGISTERS_ADDRESS: u16 = 0x4200;
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// PPU Interrupts
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pub const RDNMI: u16 = 0x4210; // V-Blank NMI Flag
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pub struct InternalRegisters {
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registers: [u8; 32],
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}
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+103
-88
@@ -1,24 +1,23 @@
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// PPU Control
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pub const INIDISP: u16 = 0x2100; // Display Control 1 (W)
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pub const TM: u16 = 0x212C; // Main Screen Designation (W)
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pub const TS: u16 = 0x212D; // Sub Screen Designation (W)
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// PPU Sprites
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pub const OBSEL: u16 = 0x2101; // Object Size and Object Base (W)
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pub const SETINI: u16 = 0x2133; // Display Control 2 (W)
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// OAM Read/Write
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pub const OAMADDL: u16 = 0x2102; // OAM Address (L)
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pub const OAMADDH: u16 = 0x2103; // OAM Address (H)
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pub const OAMDATA: u16 = 0x2104; // OAM Data Write
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// PPU BG Control
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pub const BGMODE: u16 = 0x2105; // BG Mode and BG Character Size (W)
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pub const MOSAIC: u16 = 0x2106; // Mosaic Size and Mosaic Enable (W)
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pub const BG1SC: u16 = 0x2107; // BG1 Screen Base and Screen Size (W)
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pub const BG2SC: u16 = 0x2108; // BG2 Screen Base and Screen Size (W)
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pub const BG3SC: u16 = 0x2109; // BG3 Screen Base and Screen Size (W)
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pub const BG4SC: u16 = 0x210A; // BG4 Screen Base and Screen Size (W)
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pub const BG12NBA: u16 = 0x210B; // BG Character Data Area Designation (W)
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pub const BG34NBA: u16 = 0x210C; // BG Character Data Area Designation (W)
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pub const BG1HOFS: u16 = 0x210D; // BG1 Horizontal Scroll (X) (W) and M7HOFS
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pub const BG1VOFS: u16 = 0x210E; // BG1 Vertical Scroll (Y) (W) and M7VOFS
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pub const BG2HOFS: u16 = 0x210F; // BG2 Horizontal Scroll (X) (W)
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@@ -28,58 +27,68 @@ pub const BG3VOFS: u16 = 0x2112; // BG3 Vertical Scroll (Y) (W)
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pub const BG4HOFS: u16 = 0x2113; // BG4 Horizontal Scroll (X) (W)
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pub const BG4VOFS: u16 = 0x2114; // BG4 Horizontal Scroll (X) (W)
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// PPU Rotating/Scaling
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pub const M7SEL: u16 = 0x211A; // Rotation/Scaling Mode Settings (W)
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pub const M7A: u16 = 0x211B; // Rotation/Scaling Parameter A (and Maths 16bit operand) (W)
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pub const M7B: u16 = 0x211C; // Rotation/Scaling Parameter B (and Maths 8bit operand) (W)
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pub const M7C: u16 = 0x211D; // Rotation/Scaling Parameter C (W)
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pub const M7D: u16 = 0x211E; // Rotation/Scaling Parameter D (W)
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pub const M7X: u16 = 0x211F; // Rotation/Scaling Center Coordinate X (W)
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pub const M7Y: u16 = 0x2120; // Rotation/Scaling Center Coordinate Y (W)
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// PPU Sprites
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pub const OBSEL: u16 = 0x2101; // Object Size and Object Base (W)
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// PPU Window
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pub const WH0: u16 = 0x2126; // Window 1 Left Position (X1) (W)
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pub const WH1: u16 = 0x2127; // Window 1 Right Position (X2) (W)
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pub const WH2: u16 = 0x2128; // Window 2 Left Position (X1) (W)
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pub const WH3: u16 = 0x2129; // Window 2 Right Position (X2) (W)
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pub const W12SEL: u16 = 0x2123; // Window BG1/BG2 Mask Settings (W)
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pub const W34SEL: u16 = 0x2124; // Window BG3/BG4 Mask Settings (W)
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pub const WOBJSEL: u16 = 0x2125; // Window OBJ/MATH Mask Settings (W)
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pub const WBGLOG: u16 = 0x212A; // Window 1 Mask Logic (W)
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pub const WOBJLOG: u16 = 0x212B; // Window 2 Mask Logic (W)
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pub const TMW: u16 = 0x212E; // Window Area Main Screen Disable (W)
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pub const TSW: u16 = 0x212F; // Window Area Sub Screen Disable (W)
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// PPU Interrupts
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pub const RDNMI: u16 = 0x4210; // V-Blank NMI Flag
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// PPU VRAM Access
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pub const VMAIN: u16 = 0x2115; // VRAM Address Increment
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pub const VMAINC: u16 = VMAIN; // VRAM Address Increment
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pub const VMADDL: u16 = 0x2116; // VRAM Address Low
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pub const VMADDH: u16 = 0x2117; // VRAM Address High
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pub const VMDATAL: u16 = 0x2118; // VRAM Write Low
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pub const VMDATAH: u16 = 0x2119; // VRAM Write High
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pub const VMDATALW: u16 = VMDATAL;
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pub const VMDATAHW: u16 = VMDATAH;
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// PPU Rotating/Scaling
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pub const M7SEL: u16 = 0x211A; // Rotation/Scaling Mode Settings (W)
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pub const M7A: u16 = 0x211B; // Rotation/Scaling Parameter A (and Maths 16bit operand) (W)
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pub const M7B: u16 = 0x211C; // Rotation/Scaling Parameter B (and Maths 8bit operand) (W)
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pub const M7C: u16 = 0x211D; // Rotation/Scaling Parameter C (W)
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pub const M7D: u16 = 0x211E; // Rotation/Scaling Parameter D (W)
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pub const M7X: u16 = 0x211F; // Rotation/Scaling Center Coordinate X (W)
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pub const M7Y: u16 = 0x2120; // Rotation/Scaling Center Coordinate Y (W)
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// PPU CGRAM
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pub const CGADD: u16 = 0x2121; // Palette CGRAM Address
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pub const CGDATA: u16 = 0x2122; // Palette CGRAM Address
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// PPU Window
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pub const W12SEL: u16 = 0x2123; // Window BG1/BG2 Mask Settings (W)
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pub const W34SEL: u16 = 0x2124; // Window BG3/BG4 Mask Settings (W)
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pub const WOBJSEL: u16 = 0x2125; // Window OBJ/MATH Mask Settings (W)
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pub const WH0: u16 = 0x2126; // Window 1 Left Position (X1) (W)
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pub const WH1: u16 = 0x2127; // Window 1 Right Position (X2) (W)
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pub const WH2: u16 = 0x2128; // Window 2 Left Position (X1) (W)
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pub const WH3: u16 = 0x2129; // Window 2 Right Position (X2) (W)
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pub const WBGLOG: u16 = 0x212A; // Window 1 Mask Logic (W)
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pub const WOBJLOG: u16 = 0x212B; // Window 2 Mask Logic (W)
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pub const TM: u16 = 0x212C; // Main Screen Designation (W)
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pub const TS: u16 = 0x212D; // Sub Screen Designation (W)
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pub const TMW: u16 = 0x212E; // Window Area Main Screen Disable (W)
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pub const TSW: u16 = 0x212F; // Window Area Sub Screen Disable (W)
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// PPU Color Math
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pub const CGWSEL: u16 = 0x2130; // Color Math Control Register A
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pub const CGADSUB: u16 = 0x2131; // Color Math Control Register B
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pub const COLDATA: u16 = 0x2132; // Color Math Sub Screen Backdrop Color
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// Display Control
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pub const SETINI: u16 = 0x2133; // Display Control 2 (W)
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// PPU Read-only ports
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pub const MPYL: u16 = 0x2134; // Signed Multiply Result (lower 8bit)
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pub const MPYM: u16 = 0x2135; // Signed Multiply Result (middle 8bit)
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pub const MPYH: u16 = 0x2136; // Signed Multiply Result (upper 8bit)
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pub const SLHV: u16 = 0x2137; // Latch H/V-Counter by Software (Read=Strobe)
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pub const RDOAM: u16 = 0x2138; // OAM Data Read (read-twice)
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pub const RDVRAML: u16 = 0x2139; // VRAM Read Low
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pub const RDVRAMH: u16 = 0x213A; // VRAM Read High
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pub const VMDATALR: u16 = RDVRAML;
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pub const VMDATAHR: u16 = RDVRAMH;
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pub const RDCGRAM: u16 = 0x213B; // CGRAM Data Read (Palette)(read-twice)
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pub const OPHCT: u16 = 0x213C; // Horizontal Counter Latch (read-twice)
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pub const OPVCT: u16 = 0x213D; // Vertical Counter Latch (read-twice)
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pub const STAT77: u16 = 0x213E; // PPU1 Status and PPU1 Version Number
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pub const STAT78: u16 = 0x213F; // PPU1 Status and PPU1 Version Number
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pub const MAX_BG_WIDTH: usize = 16 * 64;
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pub const MAX_BG_HEIGHT: usize = 16 * 64;
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#[derive(Debug, PartialEq, Copy, Clone)]
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pub enum TileSize {
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P8x8,
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@@ -136,7 +145,7 @@ pub enum Background {
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pub struct PPURegisters {
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data: [u8; 256],
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data: [u8; 64],
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vram: [u8; 0x10000],
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pub vblank_nmi: bool,
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pub h_count: u16,
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@@ -146,7 +155,7 @@ pub struct PPURegisters {
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impl PPURegisters {
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pub fn new() -> Self {
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Self {
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data: [0x00; 256],
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data: [0x00; 64],
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vram: [0; 0x10000],
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vblank_nmi: false,
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h_count: 0,
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@@ -163,11 +172,17 @@ impl PPURegisters {
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}
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fn _read(&self, address: u16) -> u8 {
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self.data[(address as usize) - 0x2100]
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match address {
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0x2100..=0x213F => self.data[(address as usize) - 0x2100],
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_ => 0xFF,
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}
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}
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pub fn _write(&mut self, address: u16, value: u8) {
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self.data[(address as usize) - 0x2100] = value;
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match address {
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0x2100..=0x213F => self.data[(address as usize) - 0x2100] = value,
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_ => {},
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};
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}
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pub fn read_external(&self, address: u16) -> u8 {
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@@ -177,8 +192,8 @@ impl PPURegisters {
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pub fn read(&mut self, address: u16) -> u8 {
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let result = self._read(address);
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match address {
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VMDATALR => self.handle_vram_addr_auto_increment(Some(result), None),
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VMDATAHR => self.handle_vram_addr_auto_increment(None, Some(result)),
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VMDATAL => self.handle_vram_addr_auto_increment(Some(result), None),
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VMDATAH => self.handle_vram_addr_auto_increment(None, Some(result)),
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_ => {},
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};
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self._read(address)
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@@ -186,15 +201,15 @@ impl PPURegisters {
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pub fn write(&mut self, address: u16, value: u8) {
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match address {
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VMDATALW => {
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VMDATAL => {
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self._write(address, value);
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self.handle_write_vram(Some(value), None);
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},
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VMDATAHW => {
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VMDATAH => {
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self._write(address, value);
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self.handle_write_vram(None, Some(value));
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},
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VMDATALR | VMDATAHR => {},
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RDVRAML | RDVRAMH => {},
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_ => self._write(address, value),
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};
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}
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@@ -204,17 +219,17 @@ impl PPURegisters {
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let effective_address = (address & 0x7FFF) * 2;
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if let Some(byte) = byte_lo {
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self.vram[effective_address.wrapping_add(1) as usize] = byte;
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self._write(VMDATALR, byte);
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self._write(RDVRAML, byte);
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}
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if let Some(byte) = byte_hi {
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self.vram[effective_address as usize] = byte;
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self._write(VMDATAHR, byte);
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self._write(RDVRAMH, byte);
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}
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self.handle_vram_addr_auto_increment(byte_lo, byte_hi);
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}
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fn handle_vram_addr_auto_increment(&mut self, byte_lo: Option<u8>, byte_hi: Option<u8>) {
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let register = self._read(VMAINC);
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let register = self._read(VMAIN);
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let amount_to_increment = match register & 0b11 {
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0b00 => 1,
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0b01 => 32,
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@@ -467,28 +482,28 @@ mod ppu_registers_test {
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let mut registers = PPURegisters::new();
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registers.write(VMADDL, 0x00);
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registers.write(VMADDH, 0x00);
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registers.write(VMDATAHW, 0xAB);
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registers.write(VMDATALW, 0xCD);
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registers.write(VMDATAH, 0xAB);
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registers.write(VMDATAL, 0xCD);
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assert_eq!(registers.vram[0x0000], 0xAB);
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assert_eq!(registers.vram[0x0001], 0xCD);
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registers.write(VMADDH, 0x12);
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registers.write(VMADDL, 0x34);
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registers.write(VMDATAHW, 0xAB);
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registers.write(VMDATALW, 0xCD);
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registers.write(VMDATAH, 0xAB);
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registers.write(VMDATAL, 0xCD);
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assert_eq!(registers.vram[0x2468], 0xAB);
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assert_eq!(registers.vram[0x2469], 0xCD);
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assert_eq!(registers.read(VMDATAHR), 0xAB);
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assert_eq!(registers.read(VMDATALR), 0xCD);
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assert_eq!(registers.read(RDVRAMH), 0xAB);
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assert_eq!(registers.read(RDVRAML), 0xCD);
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registers.write(VMADDH, 0xFF);
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registers.write(VMADDL, 0xFF);
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registers.write(VMDATAHW, 0xAB);
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registers.write(VMDATALW, 0xCD);
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registers.write(VMDATAH, 0xAB);
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registers.write(VMDATAL, 0xCD);
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assert_eq!(registers.vram[0xFFFE], 0xAB);
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assert_eq!(registers.vram[0xFFFF], 0xCD);
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assert_eq!(registers.read(VMDATAHR), 0xAB);
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assert_eq!(registers.read(VMDATALR), 0xCD);
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assert_eq!(registers.read(RDVRAMH), 0xAB);
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assert_eq!(registers.read(RDVRAML), 0xCD);
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}
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#[test]
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@@ -499,18 +514,18 @@ mod ppu_registers_test {
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registers.write(VMADDH, 0x00);
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// Increment when low bit is written to
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registers.write(VMAINC, 0x00);
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registers.write(VMAIN, 0x00);
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registers.write(VMDATAHW, 0xAA);
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registers.write(VMDATAH, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 0x0000);
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registers.write(VMDATALW, 0xAA);
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registers.write(VMDATAL, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 0x0001);
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// Increment when hi bit is written to
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registers.write(VMAINC, 0b1000_0000);
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registers.write(VMDATAHW, 0xAA);
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registers.write(VMAIN, 0b1000_0000);
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registers.write(VMDATAH, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 0x0002);
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registers.write(VMDATALW, 0xAA);
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registers.write(VMDATAL, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 0x0002);
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@@ -519,43 +534,43 @@ mod ppu_registers_test {
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registers.write(VMADDH, 0x00);
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// Increment when low bit is read from
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registers.write(VMAINC, 0x00);
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registers.write(VMAIN, 0x00);
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registers.read(VMDATAHR);
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registers.read(VMDATAH);
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assert_eq!(registers.get_current_vram_address(), 0x0000);
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registers.read(VMDATALR);
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registers.read(VMDATAL);
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assert_eq!(registers.get_current_vram_address(), 0x0001);
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// Increment when hi bit is read from
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registers.write(VMAINC, 0b1000_0000);
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registers.read(VMDATAHR);
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registers.write(VMAIN, 0b1000_0000);
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registers.read(VMDATAH);
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assert_eq!(registers.get_current_vram_address(), 0x0002);
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registers.read(VMDATALR);
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registers.read(VMDATAL);
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assert_eq!(registers.get_current_vram_address(), 0x0002);
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// Increment amounts
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registers.write(VMAINC, 0b1000_0000);
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registers.write(VMAIN, 0b1000_0000);
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registers.write(VMADDL, 0x00);
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registers.write(VMADDH, 0x00);
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registers.write(VMDATAHW, 0xAA);
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registers.write(VMDATAH, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 1);
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registers.write(VMAINC, 0b1000_0001);
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registers.write(VMAIN, 0b1000_0001);
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registers.write(VMADDL, 0x00);
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registers.write(VMADDH, 0x00);
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registers.write(VMDATAHW, 0xAA);
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registers.write(VMDATAH, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 32);
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registers.write(VMAINC, 0b1000_0010);
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registers.write(VMAIN, 0b1000_0010);
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registers.write(VMADDL, 0x00);
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registers.write(VMADDH, 0x00);
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registers.write(VMDATAHW, 0xAA);
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registers.write(VMDATAH, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 128);
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registers.write(VMAINC, 0b1000_0011);
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registers.write(VMAIN, 0b1000_0011);
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registers.write(VMADDL, 0x00);
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registers.write(VMADDH, 0x00);
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registers.write(VMDATAHW, 0xAA);
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registers.write(VMDATAH, 0xAA);
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assert_eq!(registers.get_current_vram_address(), 128);
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}
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