From 877b08fa26cc5f1ef34d0c45487ca3561dca5af0 Mon Sep 17 00:00:00 2001
From: Franco Colmenarez <info@francoacg.com>
Date: Sat, 30 Dec 2023 10:05:22 -0500
Subject: [PATCH] stz

---
 snes-core/src/cpu/instructionstemp/mod.rs |  1 +
 snes-core/src/cpu/instructionstemp/stz.rs | 84 +++++++++++++++++++++++
 2 files changed, 85 insertions(+)
 create mode 100644 snes-core/src/cpu/instructionstemp/stz.rs

diff --git a/snes-core/src/cpu/instructionstemp/mod.rs b/snes-core/src/cpu/instructionstemp/mod.rs
index 8743884..1fc4ff1 100644
--- a/snes-core/src/cpu/instructionstemp/mod.rs
+++ b/snes-core/src/cpu/instructionstemp/mod.rs
@@ -73,6 +73,7 @@ pub mod sta;
 pub mod stx;
 pub mod sty;
 pub mod stp;
+pub mod stz;
 pub mod bit_common;
 pub mod dec_common;
 pub mod decoder_common;
diff --git a/snes-core/src/cpu/instructionstemp/stz.rs b/snes-core/src/cpu/instructionstemp/stz.rs
new file mode 100644
index 0000000..4d59b0d
--- /dev/null
+++ b/snes-core/src/cpu/instructionstemp/stz.rs
@@ -0,0 +1,84 @@
+use crate::cpu::cycles;
+use crate::cpu::{bus::Bus, registers::Registers};
+use crate::utils::addressing::AddressingMode;
+
+use super::{CPUInstruction, Decode, write_8bit_to_address, write_16bit_to_address};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "STZ";
+
+pub struct STZ8 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for STZ8 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        write_8bit_to_address(registers, bus, self.addressing_mode, 0);
+        let (bytes, cycles) = cycles::increment_cycles_st_index(registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for STZ8 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(false, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+pub struct STZ16 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for STZ16 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        write_16bit_to_address(registers, bus, self.addressing_mode, 0);
+        let (bytes, cycles) = cycles::increment_cycles_st_index(registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for STZ16 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(true, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test_8bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.pc = 0x0000;
+        registers.set_16bit_mode(false);
+        bus.write(0x0002, 0x00);
+        bus.write(0x0001, 0x03);
+        bus.write(0x0003, 0xFF);
+        let instruction = STZ8{addressing_mode: AddressingMode::Absolute};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(bus.read(0x0003), 0x00);
+        assert_eq!(registers.pc, 0x0003);
+        assert_eq!(registers.cycles, 4);
+    }
+
+    #[test]
+    fn test_16bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.pc = 0x0000;
+        registers.set_16bit_mode(true);
+        bus.write(0x0002, 0x00);
+        bus.write(0x0001, 0x03);
+        bus.write(0x0003, 0xFF);
+        bus.write(0x0004, 0xFF);
+        let instruction = STZ16{addressing_mode: AddressingMode::Absolute};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(bus.read(0x0003), 0x00);
+        assert_eq!(bus.read(0x0004), 0x00);
+        assert_eq!(registers.pc, 0x0003);
+        assert_eq!(registers.cycles, 4);
+    }
+}