PHB

snes-core/src/cpu/cycles.rs

@@ -291,6 +291,10 @@ impl CPU {
             self.cycles += 1;
         }
     }
+
+    pub fn increment_cycles_phb(&mut self) {
+        self.registers.increment_pc(1); self.cycles += 3;
+    }
 }
 
 #[cfg(test)]

snes-core/src/cpu/instructions.rs

@@ -546,6 +546,11 @@ impl CPU {
         self.increment_cycles_pha();
     }
 
+    fn phb(&mut self, bus: &mut Bus) {
+        self.do_push(bus, &[self.registers.dbr]);
+        self.increment_cycles_phb();
+    }
+
     fn jsr(&mut self, bus: &mut Bus, addressing_mode: AddressingMode) {
         let effective_address = self.get_effective_address(bus, addressing_mode);
         let is_long = match addressing_mode {
@@ -857,6 +862,8 @@ impl CPU {
             0x62 => self.per(bus),
             // PHA
             0x48 => self.pha(bus),
+            // PHB
+            0x8B => self.phb(bus),
             _ => println!("Invalid opcode: {:02X}", opcode),
         }
     }
@@ -1733,4 +1740,18 @@ mod cpu_instructions_tests {
         assert_eq!(cpu.registers.pc, 0x0001);
         assert_eq!(cpu.cycles, 3);
     }
+
+    #[test]
+    fn test_phb() {
+        let mut cpu = CPU::new();
+        let mut bus = Bus::new();
+        cpu.registers.pc  = 0x0000;
+        cpu.registers.sp  = 0x1FC;
+        cpu.registers.dbr   = 0x12;
+        cpu.phb(&mut bus);
+        assert_eq!(bus.read(0x1FC), 0x12);
+        assert_eq!(cpu.registers.sp, 0x1FB);
+        assert_eq!(cpu.registers.pc, 0x0001);
+        assert_eq!(cpu.cycles, 3);
+    }
 }