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https://github.com/FranLMSP/snes.git
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some fixes
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@@ -1,19 +1,53 @@
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use super::registers::Registers;
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use super::{registers::Registers, bus::Bus, cycles, dma, instructions::mapper::map_opcode_to_instruction};
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pub struct CPU {
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pub struct CPU {
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pub registers: Registers,
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pub registers: Registers,
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pub cycles: usize, // TODO: remove cycles from here
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pub is_stopped: bool, // TODO: remove from here
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pub is_waiting_interrupt: bool,
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}
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}
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impl CPU {
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impl CPU {
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pub fn new() -> Self {
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pub fn new() -> Self {
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Self {
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Self {
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registers: Registers::new(),
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registers: Registers::new(),
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cycles: 0,
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is_stopped: false,
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is_waiting_interrupt: false,
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}
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}
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}
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}
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fn check_running_state(&mut self, bus: &mut Bus) -> bool {
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// Each byte in a DMA transfer takes 8 master cycles.
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// And each CPU can take either 6, 8 or 12 master cycles depending
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// on what's being read from memory. So this won't be accurate.
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if bus.dma.is_active() {
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let pending_bus_writes = bus.dma.tick();
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for (src, dst) in pending_bus_writes {
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let byte = bus.read(src);
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bus.write(dst, byte);
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let (bytes, cycles) = cycles::increment_cycles_while_stopped();
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self.registers.increment_pc(bytes); self.registers.cycles += cycles;
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}
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if !bus.dma.is_active() {
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bus.write(dma::MDMAEN as u32, 0x00)
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}
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return false;
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}
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if self.registers.is_cpu_stopped {
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let (bytes, cycles) = cycles::increment_cycles_while_stopped();
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self.registers.increment_pc(bytes); self.registers.cycles += cycles;
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return false;
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}
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if self.registers.is_cpu_waiting_interrupt {
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// TODO: check for interrupts here
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let (bytes, cycles) = cycles::increment_cycles_while_stopped();
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self.registers.increment_pc(bytes); self.registers.cycles += cycles;
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return false;
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}
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return true;
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}
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pub fn tick(&mut self, bus: &mut Bus) {
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if !self.check_running_state(bus) {
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return;
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}
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let opcode = bus.read(self.registers.get_pc_address());
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let instruction = map_opcode_to_instruction(opcode);
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instruction.execute(&mut self.registers, bus);
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}
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}
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}
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File diff suppressed because it is too large
Load Diff
+1
-1
@@ -1,4 +1,4 @@
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use crate::{utils::addressing::{AddressingMode, IndexRegister}, cpu::instructionstemp::{adc::ADC, and::AND, asl::ASL, bcc::BCC, bcs::BCS, beq::BEQ, bne::BNE, bmi::BMI, bpl::BPL, bra::BRA, brk::BRK, brl::BRL, bvc::BVC, bvs::BVS, bit::BIT, clc::CLC, cld::CLD, cli::CLI, clv::CLV, cmp::CMP, cop::COP, cpx::CPX, cpy::CPY, dec::DEC, dex::DEX, dey::DEY, eor::EOR, inc::INC, iny::INY, inx::INX, jmp::JMP, jsr::JSR, lda::LDA, ldx::LDX, ldy::LDY, lsr::LSR, mvn::MVN, mvp::MVP, nop::NOP, ora::ORA, pea::PEA, pei::PEI, per::PER, pha::PHA, phb::PHB, phd::PHD, phk::PHK, php::PHP, phx::PHX, phy::PHY, pla::PLA, plb::PLB, pld::PLD, plp::PLP, plx::PLX, ply::PLY, rep::REP, rol::ROL, ror::ROR, rti::RTI, rtl::RTL, rts::RTS, sbc::SBC, sec::SEC, sed::SED, sei::SEI, sep::SEP, sta::STA, stp::STP, stx::STX, sty::STY, stz::STZ, tax::TAX, tay::TAY, tcd::TCD, tcs::TCS, trb::TRB, tsb::TSB, tdc::TDC, tsc::TSC, tsx::TSX, txa::TXA, txs::TXS, txy::TXY, tya::TYA, tyx::TYX, wai::WAI, wdm::WDM, xba::XBA, xce::XCE}};
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use crate::{utils::addressing::{AddressingMode, IndexRegister}, cpu::instructions::{adc::ADC, and::AND, asl::ASL, bcc::BCC, bcs::BCS, beq::BEQ, bne::BNE, bmi::BMI, bpl::BPL, bra::BRA, brk::BRK, brl::BRL, bvc::BVC, bvs::BVS, bit::BIT, clc::CLC, cld::CLD, cli::CLI, clv::CLV, cmp::CMP, cop::COP, cpx::CPX, cpy::CPY, dec::DEC, dex::DEX, dey::DEY, eor::EOR, inc::INC, iny::INY, inx::INX, jmp::JMP, jsr::JSR, lda::LDA, ldx::LDX, ldy::LDY, lsr::LSR, mvn::MVN, mvp::MVP, nop::NOP, ora::ORA, pea::PEA, pei::PEI, per::PER, pha::PHA, phb::PHB, phd::PHD, phk::PHK, php::PHP, phx::PHX, phy::PHY, pla::PLA, plb::PLB, pld::PLD, plp::PLP, plx::PLX, ply::PLY, rep::REP, rol::ROL, ror::ROR, rti::RTI, rtl::RTL, rts::RTS, sbc::SBC, sec::SEC, sed::SED, sei::SEI, sep::SEP, sta::STA, stp::STP, stx::STX, sty::STY, stz::STZ, tax::TAX, tay::TAY, tcd::TCD, tcs::TCS, trb::TRB, tsb::TSB, tdc::TDC, tsc::TSC, tsx::TSX, txa::TXA, txs::TXS, txy::TXY, tya::TYA, tyx::TYX, wai::WAI, wdm::WDM, xba::XBA, xce::XCE}};
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use super::CPUInstruction;
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use super::CPUInstruction;
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