WIP script to run tests

snes-core/src/cpu/bus.rs

@@ -42,6 +42,7 @@ impl Bus {
     }
 
     fn map_address(address: u32) -> MemoryMap {
+        return MemoryMap::Cartridge;
         let (bank, sub_address) = {
             let bank = (address >> 16) as u8;
             let sub_address = address as u16;

snes-core/src/cpu/cycles.rs

@@ -108,6 +108,7 @@ fn common_conditions(cpu_registers: &Registers, addressing_mode: AddressingMode,
 
 fn common_bytes_cycles_arithmetic(addressing_mode: AddressingMode) -> (u16, usize) {
     match addressing_mode {
+        A::Accumulator                      => (1, 2),
         A::Immediate                        => (2, 2),
         A::Absolute                         => (3, 4),
         A::AbsoluteLong                     => (4, 5),

snes-core/src/rom/mod.rs

@@ -1,4 +1,5 @@
 pub mod lo_rom;
+pub mod special_ram_cart;
 
 use std::fs::File;
 use std::io::Read;

snes-core/src/rom/special_ram_cart.rs

@@ -0,0 +1,36 @@
+use super::ROM;
+
+pub struct SpecialRAMCart {
+    data: Vec<u8>,
+}
+
+impl SpecialRAMCart {
+    pub fn new() -> Self {
+        Self {
+            data: vec![0x00; 0x1000000],
+        }
+    }
+}
+
+impl ROM for SpecialRAMCart {
+    fn load(&mut self, _filename: &str) -> std::io::Result<bool> {
+        Ok(true)
+    }
+
+    fn read(&self, address: u32) -> u8 {
+        match self.data.get(address as usize) {
+            Some(byte) => *byte,
+            None => 0x00,
+        }
+    }
+
+    fn write(&mut self, address: u32, value: u8) {
+        self.data[address as usize] = value;
+    }
+}
+
+impl Default for SpecialRAMCart {
+    fn default() -> Self {
+        Self::new()
+    }
+}