tcd, tcs and tdc

snes-core/src/cpu/instructionstemp/mod.rs

@@ -76,6 +76,9 @@ pub mod stp;
 pub mod stz;
 pub mod tax;
 pub mod tay;
+pub mod tcd;
+pub mod tcs;
+pub mod tdc;
 pub mod bit_common;
 pub mod dec_common;
 pub mod decoder_common;

snes-core/src/cpu/instructionstemp/tcd.rs

@@ -0,0 +1,46 @@
+use crate::cpu::cycles;
+use crate::cpu::{bus::Bus, registers::Registers};
+
+use super::{CPUInstruction, Decode};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "TCD";
+
+pub struct TCD {}
+
+impl CPUInstruction for TCD {
+    fn execute(&self, registers: &mut Registers, _bus: &mut Bus) {
+        let result = registers.a;
+        registers.d = result;
+        registers.set_negative_flag((result >> 7) == 1);
+        registers.set_zero_flag(result == 0);
+        let (bytes, cycles) = cycles::increment_cycles_transfer();
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for TCD {
+    fn mnemonic(&self, _registers: &Registers, _bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.pc = 0x0000;
+        registers.a = 0xF0F0;
+        registers.d = 0x0000;
+        let instruction = TCD{};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.d, 0xF0F0);
+        assert_eq!(registers.pc, 0x0001);
+        assert_eq!(registers.cycles, 2);
+    }
+}

snes-core/src/cpu/instructionstemp/tcs.rs

@@ -0,0 +1,46 @@
+use crate::cpu::cycles;
+use crate::cpu::{bus::Bus, registers::Registers};
+
+use super::{CPUInstruction, Decode};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "TCS";
+
+pub struct TCS {}
+
+impl CPUInstruction for TCS {
+    fn execute(&self, registers: &mut Registers, _bus: &mut Bus) {
+        let result = registers.a;
+        registers.sp = result;
+        registers.set_negative_flag((result >> 7) == 1);
+        registers.set_zero_flag(result == 0);
+        let (bytes, cycles) = cycles::increment_cycles_transfer();
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for TCS {
+    fn mnemonic(&self, _registers: &Registers, _bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.pc = 0x0000;
+        registers.a = 0xF0F0;
+        registers.sp = 0x0000;
+        let instruction = TCS{};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.sp, 0xF0F0);
+        assert_eq!(registers.pc, 0x0001);
+        assert_eq!(registers.cycles, 2);
+    }
+}

snes-core/src/cpu/instructionstemp/tdc.rs

@@ -0,0 +1,46 @@
+use crate::cpu::cycles;
+use crate::cpu::{bus::Bus, registers::Registers};
+
+use super::{CPUInstruction, Decode};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "TDC";
+
+pub struct TDC {}
+
+impl CPUInstruction for TDC {
+    fn execute(&self, registers: &mut Registers, _bus: &mut Bus) {
+        let result = registers.d;
+        registers.a = result;
+        registers.set_negative_flag((result >> 7) == 1);
+        registers.set_zero_flag(result == 0);
+        let (bytes, cycles) = cycles::increment_cycles_transfer();
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for TDC {
+    fn mnemonic(&self, _registers: &Registers, _bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.pc = 0x0000;
+        registers.a = 0x0000;
+        registers.d = 0xF0F0;
+        let instruction = TDC{};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.a, 0xF0F0);
+        assert_eq!(registers.pc, 0x0001);
+        assert_eq!(registers.cycles, 2);
+    }
+}