rol, ror, rti, rtl, and rts instructions

2026-08-03 08:30:01 -04:00 · 2023-12-30 08:42:47 -05:00
parent 0eaf1ff0d6
commit 0150d0ef7b
6 changed files with 319 additions and 0 deletions
@@ -59,6 +59,11 @@ pub mod plp;
 pub mod plx;
 pub mod ply;
 pub mod rep;
+pub mod rol;
+pub mod ror;
+pub mod rti;
+pub mod rtl;
+pub mod rts;
 pub mod bit_common;
 pub mod dec_common;
 pub mod decoder_common;
@@ -0,0 +1,89 @@
+use crate::{cpu::{bus::Bus, registers::Registers}, utils::{alu, addressing::AddressingMode}};
+
+use crate::cpu::cycles;
+use super::{CPUInstruction, Decode, read_8bit_from_address, read_16bit_from_address, write_8bit_to_address, write_16bit_to_address};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "ROL";
+
+pub struct ROL8 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for ROL8 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        let target = read_8bit_from_address(registers, bus, self.addressing_mode);
+        let (result, affected_flags) = alu::rol(target, registers.get_carry_flag());
+        write_8bit_to_address(registers, bus, self.addressing_mode, result);
+        registers.set_flags(&affected_flags);
+        let (bytes, cycles) = cycles::increment_cycles_shift(registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for ROL8 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(false, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+pub struct ROL16 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for ROL16 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        let target = read_16bit_from_address(registers, bus, self.addressing_mode);
+        let (result, affected_flags) = alu::rol(target, registers.get_carry_flag());
+        write_16bit_to_address(registers, bus, self.addressing_mode, result);
+        registers.set_flags(&affected_flags);
+        let (bytes, cycles) = cycles::increment_cycles_shift(registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for ROL16 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(true, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test_8bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.emulation_mode = false;
+        registers.set_16bit_mode(false);
+        registers.a  = 0b0100_0000;
+        registers.pc  = 0x0000;
+        let instruction = ROL8{addressing_mode: AddressingMode::Accumulator};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.get_negative_flag(), true);
+        assert_eq!(registers.get_zero_flag(), false);
+        assert_eq!(registers.a, 0b1000_0000);
+        assert_eq!(registers.pc, 0x0001);
+        assert_eq!(registers.cycles, 2);
+    }
+
+    #[test]
+    fn test_and_16bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.emulation_mode = false;
+        registers.set_16bit_mode(true);
+        registers.a  = 0b01000000_00000000;
+        registers.pc  = 0x0000;
+        let instruction = ROL16{addressing_mode: AddressingMode::Accumulator};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.get_negative_flag(), true);
+        assert_eq!(registers.get_zero_flag(), false);
+        assert_eq!(registers.a, 0b10000000_00000000);
+        assert_eq!(registers.pc, 0x0001);
+        assert_eq!(registers.cycles, 4);
+    }
+}
@@ -0,0 +1,91 @@
+use crate::{cpu::{bus::Bus, registers::Registers}, utils::{alu, addressing::AddressingMode}};
+
+use crate::cpu::cycles;
+use super::{CPUInstruction, Decode, read_8bit_from_address, read_16bit_from_address, write_8bit_to_address, write_16bit_to_address};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "ROR";
+
+pub struct ROR8 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for ROR8 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        let target = read_8bit_from_address(registers, bus, self.addressing_mode);
+        let (result, affected_flags) = alu::ror(target, registers.get_carry_flag());
+        write_8bit_to_address(registers, bus, self.addressing_mode, result);
+        registers.set_flags(&affected_flags);
+        let (bytes, cycles) = cycles::increment_cycles_shift(registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for ROR8 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(false, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+pub struct ROR16 {
+    addressing_mode: AddressingMode,
+}
+
+impl CPUInstruction for ROR16 {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        let target = read_16bit_from_address(registers, bus, self.addressing_mode);
+        let (result, affected_flags) = alu::ror(target, registers.get_carry_flag());
+        write_16bit_to_address(registers, bus, self.addressing_mode, result);
+        registers.set_flags(&affected_flags);
+        let (bytes, cycles) = cycles::increment_cycles_shift(registers, self.addressing_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for ROR16 {
+    fn mnemonic(&self, registers: &Registers, bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_arithmetic(true, opcode, INSTR_NAME, self.addressing_mode, registers, bus)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test_8bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.emulation_mode = false;
+        registers.set_16bit_mode(false);
+        registers.set_carry_flag(true);
+        registers.a  = 0x00;
+        registers.pc  = 0x0000;
+        let instruction = ROR8{addressing_mode: AddressingMode::Accumulator};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.get_carry_flag(), false);
+        assert_eq!(registers.get_zero_flag(), false);
+        assert_eq!(registers.a, 0b1000_0000);
+        assert_eq!(registers.pc, 0x0001);
+        assert_eq!(registers.cycles, 2);
+    }
+
+    #[test]
+    fn test_and_16bit() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.emulation_mode = false;
+        registers.set_16bit_mode(true);
+        registers.set_carry_flag(true);
+        registers.a  = 0b00000000_00000000;
+        registers.pc  = 0x0000;
+        let instruction = ROR16{addressing_mode: AddressingMode::Accumulator};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.get_negative_flag(), true);
+        assert_eq!(registers.get_zero_flag(), false);
+        assert_eq!(registers.a, 0b10000000_00000000);
+        assert_eq!(registers.pc, 0x0001);
+        assert_eq!(registers.cycles, 4);
+    }
+}
@@ -0,0 +1,38 @@
+use crate::cpu::{bus::Bus, registers::Registers};
+
+use crate::cpu::cycles;
+use super::{CPUInstruction, Decode, pull_common};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "RTI";
+
+pub struct RTI {}
+
+impl CPUInstruction for RTI {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        registers.p = pull_common::do_pull(registers, bus, 1)[0];
+        let pc_bytes = pull_common::do_pull(registers, bus, 2);
+        registers.pc = (pc_bytes[0] as u16) | ((pc_bytes[1] as u16) << 8);
+        if !registers.emulation_mode {
+            registers.pbr = pull_common::do_pull(registers, bus, 1)[0];
+        }
+        let (bytes, cycles) = cycles::increment_cycles_return_interrupt(registers.emulation_mode);
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for RTI {
+    fn mnemonic(&self, _registers: &Registers, _bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+    }
+}
@@ -0,0 +1,49 @@
+use crate::cpu::{bus::Bus, registers::Registers};
+
+use crate::cpu::cycles;
+use super::{CPUInstruction, Decode, pull_common};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "RTL";
+
+pub struct RTL {}
+
+impl CPUInstruction for RTL {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        let bytes = pull_common::do_pull(registers, bus, 3);
+        // Low byte of PC is pulled first, then high byte and then PBR
+        registers.pc = (bytes[0] as u16) | ((bytes[1] as u16) << 8);
+        registers.pbr = bytes[2];
+        let (bytes, cycles) = cycles::increment_cycles_return_subroutine();
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for RTL {
+    fn mnemonic(&self, _registers: &Registers, _bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.pbr = 0x00;
+        registers.pc  = 0x0000;
+        registers.sp  = 0x1F9;
+        bus.write(0x1FC, 0x12);
+        bus.write(0x1FB, 0x34);
+        bus.write(0x1FA, 0x56);
+        let instruction = RTL{};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.pbr, 0x12);
+        assert_eq!(registers.pc, 0x3456);
+        assert_eq!(registers.cycles, 6);
+    }
+}
@@ -0,0 +1,47 @@
+use crate::cpu::{bus::Bus, registers::Registers};
+
+use crate::cpu::cycles;
+use super::{CPUInstruction, Decode, pull_common};
+use super::decoder_common;
+
+static INSTR_NAME: &'static str = "RTS";
+
+pub struct RTS {}
+
+impl CPUInstruction for RTS {
+    fn execute(&self, registers: &mut Registers, bus: &mut Bus) {
+        let bytes = pull_common::do_pull(registers, bus, 2);
+        // Low byte of PC is pulled first, then high byte
+        registers.pc = (bytes[0] as u16) | ((bytes[1] as u16) << 8);
+        let (bytes, cycles) = cycles::increment_cycles_return_subroutine();
+        registers.increment_pc(bytes); registers.cycles += cycles;
+    }
+}
+
+impl Decode for RTS {
+    fn mnemonic(&self, _registers: &Registers, _bus: &Bus, opcode: u8) -> String {
+        decoder_common::mnemonic_single_byte_instr(opcode, INSTR_NAME)
+    }
+}
+
+
+#[cfg(test)]
+mod cpu_instructions_tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+        let mut registers = Registers::new();
+        let mut bus = Bus::new();
+        registers.pbr = 0x00;
+        registers.pc  = 0x0000;
+        registers.sp  = 0x1FA;
+        bus.write(0x1FC, 0x12);
+        bus.write(0x1FB, 0x34);
+        let instruction = RTS{};
+        instruction.execute(&mut registers, &mut bus);
+        assert_eq!(registers.pbr, 0x00);
+        assert_eq!(registers.pc, 0x1234);
+        assert_eq!(registers.cycles, 6);
+    }
+}