FranLMSP/rmg-001
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Author SHA1 Message Date
FranLMSP b6b7e7bf73 Last interrupt instructions 2021-10-19 10:41:18 -05:00
FranLMSP ff9fd48190 SCF instruction 2021-10-19 10:33:43 -05:00
FranLMSP 08513ae110 CCF Instruction 2021-10-19 10:30:36 -05:00
FranLMSP ad5211d057 CPL Instruction 2021-10-19 10:24:54 -05:00
FranLMSP 7bdbfebd0e Trim some lines 2021-10-19 10:12:17 -05:00
FranLMSP 9013c09437 SET instruction 2021-10-19 10:06:22 -05:00
FranLMSP e4586db39a RES instruction 2021-10-19 10:02:43 -05:00
FranLMSP edc8429aa2 BIT instruction 2021-10-19 09:53:50 -05:00
FranLMSP a64d15c9ce SWAP instruction 2021-10-19 09:40:42 -05:00
FranLMSP d1029c1dc7 Uncommenting some asserts 2021-10-19 09:26:49 -05:00
FranLMSP 3f46ab4a54 Fix DAA instruction 2021-10-19 09:22:23 -05:00
FranLMSP f1a035d5ac WIP DAA instruction 2021-10-18 23:24:04 -05:00
FranLMSP b964992f8a Implement more JP instructions 2021-10-18 18:46:17 -05:00
FranLMSP eeeba76ebd ADD instruction bug 2021-10-18 18:18:57 -05:00
FranLMSP ac91f8f50d Fix INC and DEC 2021-10-18 17:27:46 -05:00
FranLMSP 199470cc70 RET instructions 2021-10-18 16:54:25 -05:00
FranLMSP 581e1c19d6 Bug on RET instruction 2021-10-18 13:18:15 -05:00
FranLMSP aded5fe534 ADC and SBC instructions (no tests) 2021-10-18 13:15:26 -05:00
FranLMSP 2b633c9ee0 RL and RR instructions bug 2021-10-18 12:45:16 -05:00
FranLMSP ca4a6c9f6a Bug RLA and RRA 2021-10-18 12:31:25 -05:00
FranLMSP 59acdd555e Fix SRL instruction 2021-10-18 12:03:24 -05:00
FranLMSP 9b08306c96 Temporally omitting tests for SLA and SRA 2021-10-18 10:57:06 -05:00
FranLMSP d093aa483d One more test with bus 2021-10-18 10:33:59 -05:00
FranLMSP aad827f05f RR instruction 2021-10-18 10:25:45 -05:00
FranLMSP 8d1a0f6f2f RL instruction 2021-10-18 10:13:23 -05:00
FranLMSP 9adf41ee47 16bit substraction is not really needed 2021-10-18 08:44:22 -05:00
FranLMSP 7c804029ad Some refactors 2021-10-18 08:28:19 -05:00
FranLMSP f148ee5ba6 Prefix CB RRC instruction 2021-10-17 21:45:55 -05:00
FranLMSP ec34a71fcf Mapping CB prefix instructions 2021-10-17 20:42:36 -05:00
FranLMSP 3897c3561e add and sub instructions 2021-10-17 19:14:41 -05:00
FranLMSP a8f00f46fd more CALL instructions 2021-10-17 13:12:04 -05:00
FranLMSP 31e0b2c79c Little refactor call instruction 2021-10-17 12:48:18 -05:00
FranLMSP ebadad803b Bug on LD instruction 2021-10-17 12:29:02 -05:00
FranLMSP e1d29d9530 Emulate Echo RAM 2021-10-17 12:02:33 -05:00
FranLMSP b3ba7b309e CP instruction 2021-10-17 10:55:16 -05:00
FranLMSP b098d28f0e AND, OR and XOR instructions 2021-10-16 22:38:13 -05:00
FranLMSP 12b43ee985 Fix PUSH instruction 2021-10-16 20:50:31 -05:00
FranLMSP 989971af8b Implement push and refactor pop 2021-10-16 19:41:07 -05:00
FranLMSP 4dbcb4cb6c Update readme 2021-10-16 16:33:48 -05:00
FranLMSP d24f048c86 Another LD instruction 2021-10-16 14:50:01 -05:00
FranLMSP f94314ad01 Fix some bugs and implement a way to compare the logs 2021-10-16 14:17:28 -05:00
FranLMSP 15e3d6685b Fix some bugs on instructions 2021-10-16 13:14:02 -05:00
FranLMSP afaecf597f Fix some tests, add a couple of new instructions and fix LD instruction bug 2021-10-15 20:59:35 -05:00
FranLMSP 9d8d05c660 Including more test roms and initializing the registers 2021-10-15 19:49:36 -05:00
FranLMSP f9d5cfaa02 Refactor 16bit bus read write 2021-10-15 19:18:00 -05:00
FranLMSP 891a72ad73 POP and RET instructions 2021-10-15 15:08:26 -05:00
FranLMSP 0a1edfa39e More tests for INC and DEC with 16bit registers 2021-10-15 13:44:05 -05:00
FranLMSP c55256a5b7 Refactor register bit length detection 2021-10-15 09:49:35 -05:00
FranLMSP dbe95bedf2 Increment and decrement instructions 2021-10-14 23:58:51 -05:00
FranLMSP 724cb27c49 Functions and tests for detecting half carry 2021-10-14 23:32:48 -05:00