Commit Graph

91 Commits

Author SHA1 Message Date
FranLMSP 659f602b2a Interrupts tests passing 2021-11-03 08:36:30 -05:00
FranLMSP 806a4bf211 Refactor timer 2021-11-01 22:22:43 -05:00
FranLMSP 98be8f29dd EI instruction delay and fix palette bug 2021-11-01 17:03:56 -05:00
FranLMSP aed56708fd Some refactors 2021-11-01 13:04:09 -05:00
FranLMSP b5bb582c54 Tile fetch refactor and window pixel get 2021-10-31 17:03:59 -05:00
FranLMSP 5723c3b3b6 Fix interrupts, implement halt mode and fix IME 2021-10-31 07:25:47 -05:00
FranLMSP 61db367f31 Timer implement 2021-10-30 09:13:31 -05:00
FranLMSP abbd46ebed Refactor interrupt enum 2021-10-29 18:27:21 -05:00
FranLMSP 66731e1c8e Refactor interrupt implementation 2021-10-29 17:03:02 -05:00
FranLMSP c77bc9db70 Experimental interrupts 2021-10-29 15:40:47 -05:00
FranLMSP 7f9fdc9935 PPU timings 2021-10-28 19:38:30 -05:00
FranLMSP 886fc3cd4a Rendering a basic window with pixels 2021-10-26 17:34:59 -05:00
FranLMSP d655442b9a Prevent crashing on debug 2021-10-22 09:56:54 -05:00
FranLMSP 3abdbbde85 Start modeling graphics 2021-10-21 11:06:25 -05:00
FranLMSP d2bf668bdc Reducing some warnings 2021-10-20 18:24:13 -05:00
FranLMSP 758772200f Some refactors on instructions 2021-10-20 18:16:45 -05:00
FranLMSP 09c9ef16aa Refactor parameter bytes 2021-10-20 18:03:59 -05:00
FranLMSP 72ad41f121 Implement cycle counting 2021-10-20 16:32:01 -05:00
FranLMSP aa60d8586f Update project name again 2021-10-20 14:33:11 -05:00
FranLMSP b154b4a5cb Fix some LD and rotate instructions 2021-10-20 13:39:39 -05:00
FranLMSP 82fafad9cc Fix RST instruction 2021-10-20 12:29:55 -05:00
FranLMSP 0a1f075734 Fix ADC and SBC instructions 2021-10-19 21:55:35 -05:00
FranLMSP 39ea049fda Fix many signed ADD 2021-10-19 20:10:17 -05:00
FranLMSP fade566d12 Overflow bug 2021-10-19 14:34:23 -05:00
FranLMSP 3b81d34d71 More bugs on add instructions 2021-10-19 14:33:11 -05:00
FranLMSP 8b287c17c7 Fix ADD carry 2021-10-19 13:59:53 -05:00
FranLMSP 6b1d50ba76 Prevent panic on adding or sub with overflow on CPU 2021-10-19 13:17:14 -05:00
FranLMSP f928207a8d 0xF8 instruction 2021-10-19 11:04:52 -05:00
FranLMSP b6b7e7bf73 Last interrupt instructions 2021-10-19 10:41:18 -05:00
FranLMSP ff9fd48190 SCF instruction 2021-10-19 10:33:43 -05:00
FranLMSP 08513ae110 CCF Instruction 2021-10-19 10:30:36 -05:00
FranLMSP ad5211d057 CPL Instruction 2021-10-19 10:24:54 -05:00
FranLMSP 7bdbfebd0e Trim some lines 2021-10-19 10:12:17 -05:00
FranLMSP 9013c09437 SET instruction 2021-10-19 10:06:22 -05:00
FranLMSP e4586db39a RES instruction 2021-10-19 10:02:43 -05:00
FranLMSP edc8429aa2 BIT instruction 2021-10-19 09:53:50 -05:00
FranLMSP a64d15c9ce SWAP instruction 2021-10-19 09:40:42 -05:00
FranLMSP d1029c1dc7 Uncommenting some asserts 2021-10-19 09:26:49 -05:00
FranLMSP 3f46ab4a54 Fix DAA instruction 2021-10-19 09:22:23 -05:00
FranLMSP f1a035d5ac WIP DAA instruction 2021-10-18 23:24:04 -05:00
FranLMSP b964992f8a Implement more JP instructions 2021-10-18 18:46:17 -05:00
FranLMSP eeeba76ebd ADD instruction bug 2021-10-18 18:18:57 -05:00
FranLMSP ac91f8f50d Fix INC and DEC 2021-10-18 17:27:46 -05:00
FranLMSP 199470cc70 RET instructions 2021-10-18 16:54:25 -05:00
FranLMSP 581e1c19d6 Bug on RET instruction 2021-10-18 13:18:15 -05:00
FranLMSP aded5fe534 ADC and SBC instructions (no tests) 2021-10-18 13:15:26 -05:00
FranLMSP 2b633c9ee0 RL and RR instructions bug 2021-10-18 12:45:16 -05:00
FranLMSP ca4a6c9f6a Bug RLA and RRA 2021-10-18 12:31:25 -05:00
FranLMSP 59acdd555e Fix SRL instruction 2021-10-18 12:03:24 -05:00
FranLMSP 9b08306c96 Temporally omitting tests for SLA and SRA 2021-10-18 10:57:06 -05:00