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Refactor interrupt implementation

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This commit is contained in:
Franco Colmenarez
2021-10-29 17:03:02 -05:00
parent c77bc9db70
commit 66731e1c8e
3 changed files with 25 additions and 25 deletions
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src/bus.rs
+2 -2
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@@ -91,11 +91,11 @@ impl Bus {
pub fn write(&mut self, address: u16, data: u8) {
if address == 0xFF01 {
print!("{}", data as char);
// print!("{}", data as char);
}
if BANK_ZERO.in_range(address) || BANK_SWITCHABLE.in_range(address) {
println!("WRITING TO ROM");
// println!("WRITING TO ROM");
} else if WORK_RAM_1.in_range(address) || WORK_RAM_2.in_range(address) {
self.data[address as usize] = data;
// Copy to the ECHO RAM